[coreboot] PCI register read/mod/write code
Peter Stuge
peter at stuge.se
Tue Oct 5 03:45:17 CEST 2010
ron minnich wrote:
> > dword = pci_read_config8(dev, 0x64);
> > dword |= 1 << 10;
> > pci_write_config8(dev, 0x64, dword);
>
> Actually, I don't even have a problem with this construct. Why?
> Because it's in just about every kernel I've ever worked with.
> It's a common technique.
Other kids doing it isn't neccessarily a good reason.
> simple
> complex
> mixed idioms.
I think the ratio of simple vs. complex operations is significant.
The majority I've seen in the code are simple, but granted I haven't
read every file. I agree that mixed idioms are annoying if nothing
else, but I think the benefit from replacing all the simple cases is
important enough to do it.
Those complex cases will stand out more and may thus get more careful
review, hopefully finding bugs earlier. There's a high ratio of noise
and repetition in the quoted code.
> It's a good idea for our code base to adhere to such common idioms.
> It makes for an easier time for people coming in from, e.g., Linux.
> I don't find the functions easier.
Maybe we could try them on for size for a while anyway? I wrote a
semantic patch to have coccinelle do this change. The spatch isn't
complete however, I should also try to make it remove variables that
are now unused. Anyway, both .cocci and resulting .patch are
attached.
I was surprised but happy to discover that comments in the third file
src/cpu/amd/quadcore/quadcore.c actually match the code almost word
for word after the change. Apparently I'm not completely alone in my
way of thinking about these things. ;)
Testing this it became obvious why I prefer set and clear: they take
un-modified bits as input, whereas pci_and8() would require callers
to do the ~() trick, which I also think is very nice to get rid of.
Commands used to generate patch and diffstat:
grep -lr =.*pci_read_config src|grep -v '/\.svn/'|uniq|xargs spatch -sp_file pci_set_clear.cocci > pci_set_clear.patch
sed -e '/^---/{h;d}' -e '/^+++/{p;x}' -e 's,^--- src/,+++ src/,' pci_set_clear.patch |sed 's,^+++ /tmp,--- /tmp,'|diffstat > pci_set_clear.diffstat
> Also, as pointed out, the proposed functions solve one special case.
> Better to fix the real problem, which is that the compiler can tell
> us about this type of error but we're not letting it. That will fix
> all such problems, not just the pci subsystem.
I completely agree that we need to get the deal with warnings sorted.
I will admit that I used the bug a little bit as an excuse to bring
these functions up again, because I associated strongly when looking
at the bug.
//Peter
-------------- next part --------------
@ doubleor8 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config8(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
pci_write_config8(dev, reg, tmp);
@ doubleand8 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config8(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
pci_write_config8(dev, reg, tmp);
@ set8 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config8(dev, reg);
- tmp |= val;
- pci_write_config8(dev, reg, tmp);
+ pci_set8(dev, reg, val);
@ clear8 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config8(dev, reg);
- tmp &= ~val;
- pci_write_config8(dev, reg, tmp);
+ pci_clear8(dev, reg, val);
@ doubleor16 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config16(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
pci_write_config16(dev, reg, tmp);
@ doubleand16 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config16(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
pci_write_config16(dev, reg, tmp);
@ set16 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config16(dev, reg);
- tmp |= val;
- pci_write_config16(dev, reg, tmp);
+ pci_set16(dev, reg, val);
@ clear16 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config16(dev, reg);
- tmp &= ~val;
- pci_write_config16(dev, reg, tmp);
+ pci_clear16(dev, reg, val);
@ doubleor32 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config32(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
pci_write_config32(dev, reg, tmp);
@ doubleand32 @
expression tmp, dev, reg, val, val2;
@@
tmp = pci_read_config32(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
pci_write_config32(dev, reg, tmp);
@ set32 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config32(dev, reg);
- tmp |= val;
- pci_write_config32(dev, reg, tmp);
+ pci_set32(dev, reg, val);
@ clear32 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config32(dev, reg);
- tmp &= ~val;
- pci_write_config32(dev, reg, tmp);
+ pci_clear32(dev, reg, val);
-------------- next part --------------
Incomplete proof of concept patch. NOT! Signed off.
cpu/amd/dualcore/amd_sibling.c | 4
cpu/amd/dualcore/dualcore.c | 8 -
cpu/amd/model_10xxx/init_cpus.c | 8 -
cpu/amd/model_fxx/fidvid.c | 4
cpu/amd/quadcore/amd_sibling.c | 4
cpu/amd/quadcore/quadcore.c | 8 -
devices/hypertransport.c | 4
devices/pci_device.c | 4
devices/pciexp_device.c | 4
drivers/sil/3114/sil_sata.c | 8 -
mainboard/amd/dbm690t/mainboard.c | 8 -
mainboard/amd/mahogany/mainboard.c | 5 -
mainboard/amd/mahogany_fam10/mainboard.c | 5 -
mainboard/amd/pistachio/mainboard.c | 16 ---
mainboard/amd/tilapia_fam10/mainboard.c | 21 ----
mainboard/arima/hdama/mptable.c | 4
mainboard/asus/a8n_e/romstage.c | 8 -
mainboard/asus/a8v-e_se/romstage.c | 4
mainboard/asus/m2v-mx_se/romstage.c | 5 -
mainboard/asus/m4a785-m/mainboard.c | 13 --
mainboard/broadcom/blast/mptable.c | 4
mainboard/dell/s1850/romstage.c | 36 ++------
mainboard/dell/s1850/watchdog.c | 4
mainboard/getac/p470/romstage.c | 20 +---
mainboard/gigabyte/ga_2761gxdk/romstage.c | 16 +--
mainboard/gigabyte/m57sli/romstage.c | 16 +--
mainboard/gigabyte/ma785gmt/mainboard.c | 21 ----
mainboard/gigabyte/ma78gm/mainboard.c | 5 -
mainboard/hp/dl145_g3/mptable.c | 8 -
mainboard/hp/dl165_g6_fam10/mptable.c | 8 -
mainboard/ibase/mb899/romstage.c | 20 +---
mainboard/intel/d945gclf/romstage.c | 20 +---
mainboard/intel/jarrell/jarrell_fixups.c | 4
mainboard/intel/jarrell/watchdog.c | 16 ---
mainboard/jetway/pa78vm5/mainboard.c | 5 -
mainboard/kontron/986lcd-m/romstage.c | 20 +---
mainboard/kontron/kt690/mainboard.c | 8 -
mainboard/msi/ms7135/romstage.c | 9 --
mainboard/msi/ms7260/romstage.c | 16 +--
mainboard/msi/ms9185/mptable.c | 4
mainboard/msi/ms9282/romstage.c | 4
mainboard/msi/ms9652_fam10/romstage.c | 4
mainboard/nvidia/l1_2pvv/romstage.c | 16 +--
mainboard/roda/rk886ex/romstage.c | 20 +---
mainboard/sunw/ultra40/romstage.c | 4
mainboard/supermicro/h8dme/romstage.c | 16 +--
mainboard/supermicro/h8dmr/romstage.c | 16 +--
mainboard/supermicro/h8dmr_fam10/romstage.c | 16 +--
mainboard/supermicro/h8qme_fam10/romstage.c | 16 +--
mainboard/supermicro/x6dai_g/watchdog.c | 4
mainboard/supermicro/x6dhe_g/watchdog.c | 4
mainboard/supermicro/x6dhe_g2/watchdog.c | 4
mainboard/supermicro/x6dhr_ig/watchdog.c | 4
mainboard/supermicro/x6dhr_ig2/watchdog.c | 4
mainboard/technexion/tim5690/mainboard.c | 4
mainboard/technexion/tim5690/tn_post_code.c | 40 ++-------
mainboard/technexion/tim8690/mainboard.c | 13 --
mainboard/tyan/s2891/romstage.c | 13 --
mainboard/tyan/s2892/romstage.c | 10 --
mainboard/tyan/s2895/romstage.c | 16 +--
mainboard/tyan/s2912/romstage.c | 17 +--
mainboard/tyan/s2912_fam10/romstage.c | 17 +--
mainboard/via/epia-m/romstage.c | 5 -
mainboard/via/epia-m700/romstage.c | 4
mainboard/via/epia-n/romstage.c | 5 -
mainboard/via/epia/romstage.c | 5 -
mainboard/via/vt8454c/romstage.c | 4
northbridge/amd/amdfam10/misc_control.c | 4
northbridge/amd/amdfam10/reset_test.c | 4
northbridge/amd/amdk8/coherent_ht.c | 10 --
northbridge/amd/amdk8/exit_from_self.c | 18 ----
northbridge/amd/amdk8/incoherent_ht.c | 4
northbridge/amd/amdk8/misc_control.c | 13 --
northbridge/amd/amdk8/raminit.c | 8 -
northbridge/amd/amdk8/raminit_f.c | 22 +----
northbridge/amd/amdk8/raminit_f_dqs.c | 16 ---
northbridge/amd/amdk8/reset_test.c | 8 -
northbridge/intel/e7501/raminit.c | 34 ++-----
northbridge/intel/e7520/raminit.c | 4
northbridge/intel/e7525/raminit.c | 4
northbridge/intel/i3100/raminit.c | 4
northbridge/intel/i82830/raminit.c | 13 --
northbridge/intel/i855/raminit.c | 4
northbridge/intel/i945/early_init.c | 24 +----
northbridge/intel/i945/raminit.c | 31 +------
northbridge/via/cn400/agp.c | 4
northbridge/via/cn400/northbridge.c | 12 --
northbridge/via/cn400/raminit.c | 8 -
northbridge/via/cn400/vlink.c | 16 ---
northbridge/via/cn700/agp.c | 4
northbridge/via/cn700/northbridge.c | 8 -
northbridge/via/cx700/cx700_agp.c | 8 -
northbridge/via/cx700/cx700_lpc.c | 24 +----
northbridge/via/cx700/cx700_sata.c | 20 +---
northbridge/via/cx700/cx700_usb.c | 4
northbridge/via/cx700/raminit.c | 40 ++-------
northbridge/via/vx800/dev_init.c | 80 ++++--------------
northbridge/via/vx800/driving_setting.c | 12 --
northbridge/via/vx800/examples/romstage.c | 4
northbridge/via/vx800/rank_map.c | 8 -
northbridge/via/vx800/uma_ram_setting.c | 13 --
northbridge/via/vx800/vx800_lpc.c | 28 +-----
southbridge/amd/amd8111/amd8111_acpi.c | 4
southbridge/amd/amd8111/amd8111_early_ctrl.c | 4
southbridge/amd/amd8111/amd8111_lpc.c | 21 +---
southbridge/amd/amd8111/amd8111_pci.c | 5 -
southbridge/amd/amd8131/amd8131_bridge.c | 32 +------
southbridge/amd/amd8132/amd8132_bridge.c | 33 +------
southbridge/amd/amd8151/amd8151_agp3.c | 8 -
southbridge/amd/cs5530/cs5530_enable_rom.c | 4
southbridge/amd/cs5536/cs5536_ide.c | 4
southbridge/amd/rs690/rs690.c | 8 -
southbridge/amd/rs690/rs690_gfx.c | 8 -
southbridge/amd/rs690/rs690_ht.c | 9 --
southbridge/amd/rs690/rs690_pcie.c | 27 +-----
southbridge/amd/rs780/rs780.c | 16 ---
southbridge/amd/rs780/rs780_early_setup.c | 12 --
southbridge/amd/rs780/rs780_gfx.c | 9 --
southbridge/amd/rs780/rs780_ht.c | 9 --
southbridge/amd/sb600/sb600_early_setup.c | 92 +++++----------------
southbridge/amd/sb600/sb600_ide.c | 12 --
southbridge/amd/sb600/sb600_lpc.c | 16 ---
southbridge/amd/sb600/sb600_pci.c | 64 +++-----------
southbridge/amd/sb600/sb600_sata.c | 38 ++------
southbridge/amd/sb600/sb600_sm.c | 14 ---
southbridge/amd/sb600/sb600_usb.c | 32 +------
southbridge/amd/sb700/sb700_early_setup.c | 80 ++++--------------
southbridge/amd/sb700/sb700_ide.c | 16 ---
southbridge/amd/sb700/sb700_lpc.c | 16 ---
southbridge/amd/sb700/sb700_pci.c | 57 ++-----------
southbridge/amd/sb700/sb700_sata.c | 34 +------
southbridge/amd/sb700/sb700_sm.c | 26 +----
southbridge/amd/sb700/sb700_usb.c | 20 +---
southbridge/broadcom/bcm21000/bcm21000_pcie.c | 9 --
southbridge/broadcom/bcm5780/bcm5780_pcie.c | 5 -
southbridge/broadcom/bcm5785/bcm5785_early_setup.c | 34 +------
southbridge/broadcom/bcm5785/bcm5785_enable_rom.c | 4
southbridge/broadcom/bcm5785/bcm5785_sata.c | 4
southbridge/broadcom/bcm5785/bcm5785_usb.c | 4
southbridge/intel/esb6300/esb6300_lpc.c | 13 --
southbridge/intel/esb6300/esb6300_pci.c | 8 -
southbridge/intel/esb6300/esb6300_pic.c | 4
southbridge/intel/i3100/i3100_lpc.c | 8 -
southbridge/intel/i82371eb/i82371eb_early_pm.c | 8 -
southbridge/intel/i82371eb/i82371eb_early_smbus.c | 8 -
southbridge/intel/i82801ax/i82801ax_pci.c | 10 --
southbridge/intel/i82801ax/i82801ax_watchdog.c | 4
southbridge/intel/i82801bx/i82801bx_pci.c | 10 --
southbridge/intel/i82801bx/i82801bx_watchdog.c | 4
southbridge/intel/i82801dx/i82801dx_pci.c | 5 -
southbridge/intel/i82801dx/i82801dx_smihandler.c | 8 -
southbridge/intel/i82801ex/i82801ex_lpc.c | 16 ---
southbridge/intel/i82801ex/i82801ex_pci.c | 8 -
southbridge/intel/i82801ex/i82801ex_watchdog.c | 4
southbridge/intel/i82801gx/i82801gx.c | 4
southbridge/intel/i82801gx/i82801gx_azalia.c | 12 --
southbridge/intel/i82801gx/i82801gx_lpc.c | 4
southbridge/intel/i82801gx/i82801gx_pci.c | 9 --
southbridge/intel/i82801gx/i82801gx_pcie.c | 16 ---
southbridge/intel/i82801gx/i82801gx_sata.c | 12 --
southbridge/intel/i82801gx/i82801gx_smihandler.c | 4
southbridge/intel/i82801gx/i82801gx_usb.c | 4
southbridge/intel/i82801gx/i82801gx_usb_ehci.c | 15 ---
southbridge/intel/i82801gx/i82801gx_watchdog.c | 4
southbridge/intel/pxhd/pxhd_bridge.c | 4
southbridge/nvidia/ck804/ck804.c | 6 -
southbridge/nvidia/ck804/ck804_enable_rom.c | 4
southbridge/nvidia/ck804/ck804_ide.c | 4
southbridge/nvidia/ck804/ck804_lpc.c | 12 --
southbridge/nvidia/ck804/ck804_pci.c | 9 --
southbridge/nvidia/ck804/ck804_pcie.c | 5 -
southbridge/nvidia/ck804/ck804_sata.c | 4
southbridge/nvidia/ck804/ck804_usb2.c | 4
southbridge/nvidia/mcp55/mcp55.c | 4
southbridge/nvidia/mcp55/mcp55_azalia.c | 12 --
southbridge/nvidia/mcp55/mcp55_early_setup_car.c | 8 -
southbridge/nvidia/mcp55/mcp55_enable_rom.c | 12 --
southbridge/nvidia/mcp55/mcp55_ide.c | 4
southbridge/nvidia/mcp55/mcp55_lpc.c | 8 -
southbridge/nvidia/mcp55/mcp55_pci.c | 14 ---
southbridge/nvidia/mcp55/mcp55_pcie.c | 5 -
southbridge/nvidia/mcp55/mcp55_sata.c | 4
southbridge/nvidia/mcp55/mcp55_usb2.c | 4
southbridge/sis/sis966/sis966.c | 4
southbridge/sis/sis966/sis966_early_setup_car.c | 8 -
southbridge/sis/sis966/sis966_ide.c | 4
southbridge/sis/sis966/sis966_lpc.c | 8 -
southbridge/sis/sis966/sis966_nic.c | 4
southbridge/sis/sis966/sis966_pcie.c | 5 -
southbridge/ti/pci7420/pci7420_cardbus.c | 8 -
southbridge/via/k8t890/k8t890_bridge.c | 4
southbridge/via/k8t890/k8t890_ctrl.c | 8 -
southbridge/via/k8t890/k8t890_early_car.c | 4
southbridge/via/k8t890/k8t890_host.c | 12 --
southbridge/via/k8t890/k8t890_traf_ctrl.c | 5 -
southbridge/via/vt8231/vt8231.c | 4
southbridge/via/vt8231/vt8231_early_serial.c | 4
southbridge/via/vt8231/vt8231_early_smbus.c | 8 -
southbridge/via/vt8231/vt8231_ide.c | 4
southbridge/via/vt8231/vt8231_lpc.c | 20 +---
southbridge/via/vt8231/vt8231_nic.c | 4
southbridge/via/vt8235/vt8235.c | 8 -
southbridge/via/vt8235/vt8235_ide.c | 4
southbridge/via/vt8235/vt8235_lpc.c | 24 +----
southbridge/via/vt8235/vt8235_nic.c | 4
southbridge/via/vt8237r/vt8237_ctrl.c | 12 --
southbridge/via/vt8237r/vt8237r_early_smbus.c | 4
southbridge/via/vt8237r/vt8237r_ide.c | 8 -
southbridge/via/vt8237r/vt8237r_lpc.c | 32 +------
southbridge/via/vt8237r/vt8237r_sata.c | 4
southbridge/via/vt8237r/vt8237r_usb.c | 8 -
211 files changed, 644 insertions(+), 1909 deletions(-)
--- src/cpu/amd/model_10xxx/init_cpus.c 2010-10-01 09:27:05.000000000 +0200
+++ /tmp/cocci-output-5159-af6345-init_cpus.c 2010-10-05 03:02:08.273450418 +0200
@@ -238,9 +238,7 @@ static void enable_apic_ext_id(u32 node)
{
u32 val;
- val = pci_read_config32(NODE_HT(node), 0x68);
- val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
- pci_write_config32(NODE_HT(node), 0x68, val);
+ pci_set32(NODE_HT(node), 0x68, (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST));
}
static void STOP_CAR_AND_CPU(void)
@@ -426,9 +424,7 @@ static void start_node(u8 node)
#endif
/* Allow APs to make requests (ROM fetch) */
- val = pci_read_config32(NODE_HT(node), 0x6c);
- val &= ~(1 << 1);
- pci_write_config32(NODE_HT(node), 0x6c, val);
+ pci_clear32(NODE_HT(node), 0x6c, (1 << 1));
printk(BIOS_DEBUG, " done.\n");
}
--- src/cpu/amd/model_fxx/fidvid.c 2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-f90259-fidvid.c 2010-10-05 03:02:09.512443971 +0200
@@ -52,9 +52,7 @@ static void enable_fid_change(void)
/* disable the DRAM interface at first, it will be enabled
* by raminit again */
- dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94);
- dword |= (1 << 14);
- pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword);
+ pci_set32(PCI_DEV(0, 0x18 + i, 2), 0x94, (1 << 14));
dword = 0x23070700; /* enable FID/VID change */
// dword = 0x00070000; /* enable FID/VID change */
--- src/cpu/amd/quadcore/quadcore.c 2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-188a6a-quadcore.c 2010-10-05 03:02:10.440443856 +0200
@@ -69,13 +69,9 @@ static void real_start_other_core(u32 no
/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
accesses and error logging to core0 */
- dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
- dword |= 1 << 27; // NbMcaToMstCpuEn bit
- pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
+ pci_set32(NODE_PCI(nodeid, 3), 0x44, 1 << 27);
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
- dword |= 1 << 5;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
+ pci_set32(NODE_PCI(nodeid, 0), 0x68, 1 << 5);
if(cores > 1) {
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
--- src/cpu/amd/quadcore/amd_sibling.c 2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-af31e0-amd_sibling.c 2010-10-05 03:02:10.736445301 +0200
@@ -67,9 +67,7 @@ static void enable_apic_ext_id(u32 nodes
for(nodeid=0; nodeid<nodes; nodeid++){
u32 val;
dev = get_node_pci(nodeid, 0);
- val = pci_read_config32(dev, 0x68);
- val |= (1<<17)|(1<<18);
- pci_write_config32(dev, 0x68, val);
+ pci_set32(dev, 0x68, (1 << 17) | (1 << 18));
}
}
--- src/cpu/amd/dualcore/dualcore.c 2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-6d84dc-dualcore.c 2010-10-05 03:02:11.032443892 +0200
@@ -45,13 +45,9 @@ static inline void real_start_other_core
{
uint32_t dword;
// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
- dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
- dword |= 1<<27; // NbMcaToMstCpuEn bit
- pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
+ pci_set32(PCI_DEV(0, 0x18 + nodeid, 3), 0x44, 1 << 27);
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
- dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
- dword |= 1<<5;
- pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
+ pci_set32(PCI_DEV(0, 0x18 + nodeid, 0), 0x68, 1 << 5);
}
//it is running on core0 of node0
--- src/cpu/amd/dualcore/amd_sibling.c 2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-4258ec-amd_sibling.c 2010-10-05 03:02:11.304444501 +0200
@@ -45,9 +45,7 @@ static void enable_apic_ext_id(int nodes
for(nodeid=0; nodeid<nodes; nodeid++){
uint32_t val;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
- val = pci_read_config32(dev, 0x68);
- val |= (1<<17)|(1<<18);
- pci_write_config32(dev, 0x68, val);
+ pci_set32(dev, 0x68, (1 << 17) | (1 << 18));
}
}
--- src/devices/pciexp_device.c 2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-869853-pciexp_device.c 2010-10-05 03:02:11.676444238 +0200
@@ -40,9 +40,7 @@ static void pciexp_tune_dev(device_t dev
// TODO make this depending on ASPM
/* Enable ASPM Role Based Error Reporting */
u32 reg32;
- reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
- reg32 |= PCI_EXP_DEVCAP_RBER;
- pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+ pci_set32(dev, cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
#endif
}
--- src/devices/hypertransport.c 2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-a94e33-hypertransport.c 2010-10-05 03:02:12.072452863 +0200
@@ -368,9 +368,7 @@ static void ht_collapse_early_enumeratio
}
/* Clear the unitid */
- flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
- flags &= ~0x1f;
- pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
+ pci_clear16(&dummy, pos + PCI_CAP_FLAGS, 0x1f);
printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
dev_path(&dummy), dummy.vendor, dummy.device);
}
--- src/devices/pci_device.c 2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-69ea6d-pci_device.c 2010-10-05 03:02:12.976444094 +0200
@@ -626,9 +626,7 @@ void pci_bus_enable_resources(struct dev
void pci_bus_reset(struct bus *bus)
{
unsigned ctl;
- ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
- ctl |= PCI_BRIDGE_CTL_BUS_RESET;
- pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
+ pci_set16(bus->dev, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
mdelay(10);
ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
--- src/drivers/sil/3114/sil_sata.c 2010-10-01 09:27:15.000000000 +0200
+++ /tmp/cocci-output-5159-569390-sil_sata.c 2010-10-05 03:02:14.212452144 +0200
@@ -19,16 +19,12 @@ static void si_sata_init(struct device *
{
uint32_t dword;
/* enable change device id and class id */
- dword = pci_read_config32(dev,0x40);
- dword |= (1<<0);
- pci_write_config32(dev, 0x40, dword);
+ pci_set32(dev, 0x40, (1 << 0));
/* Set IDE Class, Native mode, two drives per channel */
dword = 0x01018f00;
pci_write_config32(dev, 0x08, dword);
/* disable change device id and class id*/
- dword = pci_read_config32(dev,0x40);
- dword &= ~(1<<0);
- pci_write_config32(dev, 0x40, dword);
+ pci_clear32(dev, 0x40, (1 << 0));
printk(BIOS_INFO, "SIL3114 set to IDE compatible mode\n");
}
--- src/northbridge/amd/amdk8/raminit_f.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-1b9604-raminit_f.c 2010-10-05 03:02:14.452444680 +0200
@@ -891,9 +891,7 @@ static void set_dimm_size(const struct m
#endif
if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
- dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
- dword &= ~(ClkDis0 >> index);
- pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
+ pci_clear32(ctrl->f2, DRAM_CTRL_MISC, (ClkDis0 >> index));
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
@@ -1523,9 +1521,7 @@ static long spd_enable_2channels(const s
/* mux capable and single dimm in channelB */
if (mux_cap) {
printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
- dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
- dcm |= DCM_Mode64BitMux;
- pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
+ pci_set32(ctrl->f2, DRAM_CTRL_MISC, DCM_Mode64BitMux);
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
//dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@@ -2217,9 +2213,7 @@ static void set_4RankRDimm(const struct
if (value == 1) {
uint32_t dch;
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
- dch |= DCH_FourRankRDimm;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_set32(ctrl->f2, DRAM_CONFIG_HIGH, DCH_FourRankRDimm);
}
#endif
}
@@ -2494,11 +2488,7 @@ static void set_SlowAccessMode(const str
{
uint32_t dch;
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-
- dch |= (1<<20);
-
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_set32(ctrl->f2, DRAM_CONFIG_HIGH, (1 << 20));
}
#endif
@@ -3079,9 +3069,7 @@ static void sdram_enable(int controllers
//Rev F0/F1 workaround
#if 1
/* Set the DqsRcvEnTrain bit */
- dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
- dword |= DC_DqsRcvEnTrain;
- pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
+ pci_set32(ctrl[i].f2, DRAM_CTRL, DC_DqsRcvEnTrain);
#endif
tsc0[i] = rdtsc();
}
--- src/northbridge/amd/amdk8/raminit_f_dqs.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-2c5361-raminit_f_dqs.c 2010-10-05 03:02:17.756443856 +0200
@@ -556,9 +556,7 @@ static unsigned TrainRcvrEn(const struct
{
#if 1
/* Set the DqsRcvEnTrain bit */
- dword = pci_read_config32(ctrl->f2, DRAM_CTRL);
- dword |= DC_DqsRcvEnTrain;
- pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
+ pci_set32(ctrl->f2, DRAM_CTRL, DC_DqsRcvEnTrain);
#endif
}
}
@@ -841,9 +839,7 @@ static unsigned TrainRcvrEn(const struct
if(!cpu_f0_f1)
#endif
{
- dword = pci_read_config32(ctrl->f2, DRAM_CTRL);
- dword &= ~DC_DqsRcvEnTrain;
- pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
+ pci_clear32(ctrl->f2, DRAM_CTRL, DC_DqsRcvEnTrain);
}
}
@@ -1572,13 +1568,9 @@ static void f0_svm_workaround(int contro
if(!cpu_f0_f1[i]) continue;
- dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
- dword &= ~DC_DqsRcvEnTrain;
- pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
+ pci_clear32(ctrl[i].f2, DRAM_CTRL, DC_DqsRcvEnTrain);
- dword = pci_read_config32(ctrl[i].f2, DRAM_INIT);
- dword |= DI_EnDramInit;
- pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
+ pci_set32(ctrl[i].f2, DRAM_INIT, DI_EnDramInit);
dword &= ~DI_EnDramInit;
pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
--- src/northbridge/amd/amdk8/reset_test.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-e2ab30-reset_test.c 2010-10-05 03:02:20.976444101 +0200
@@ -39,17 +39,13 @@ static inline void distinguish_cpu_reset
u32 htic;
device_t device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
- htic = pci_read_config32(device, HT_INIT_CONTROL);
- htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
- pci_write_config32(device, HT_INIT_CONTROL, htic);
+ pci_set32(device, HT_INIT_CONTROL, HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect);
}
static void set_bios_reset(void)
{
u32 htic;
- htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+ pci_clear32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, HTIC_BIOSR_Detect);
}
static unsigned node_link_to_bus(unsigned node, unsigned link)
--- src/northbridge/amd/amdk8/raminit.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-254824-raminit.c 2010-10-05 03:02:21.308443845 +0200
@@ -1833,9 +1833,7 @@ static int update_dimm_ecc(const struct
return -1;
}
if (value != 2) {
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
- dcl &= ~DCL_DimmEccEn;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_clear32(ctrl->f2, DRAM_CONFIG_LOW, DCL_DimmEccEn);
}
return 1;
}
@@ -2249,9 +2247,7 @@ static void sdram_enable(int controllers
else {
/* Disable dram receivers */
uint32_t dcl;
- dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
- dcl |= DCL_DisInRcvrs;
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_set32(ctrl[i].f2, DRAM_CONFIG_LOW, DCL_DisInRcvrs);
}
}
--- src/northbridge/amd/amdk8/incoherent_ht.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-bc211a-incoherent_ht.c 2010-10-05 03:02:25.092449188 +0200
@@ -116,9 +116,7 @@ static void ht_collapse_previous_enumera
}
/* Clear the unitid */
- flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
- flags &= ~0x1f;
- pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+ pci_clear16(dev, pos + PCI_CAP_FLAGS, 0x1f);
}
}
--- src/northbridge/amd/amdk8/coherent_ht.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-36d3bc-coherent_ht.c 2010-10-05 03:02:26.300443882 +0200
@@ -147,11 +147,7 @@ static void disable_probes(void)
print_spew("Disabling read/write/fill probes for UP... ");
- val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
- val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
- HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
- HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
- pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
+ pci_set32(NODE_HT(0), HT_TRANSACTION_CONTROL, HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P);
print_spew("done.\n");
@@ -202,9 +198,7 @@ static void enable_routing(u8 node)
print_spew("Enabling routing table for node ");
print_spew_hex8(node);
- val=pci_read_config32(NODE_HT(node), 0x6c);
- val &= ~((1<<1)|(1<<0));
- pci_write_config32(NODE_HT(node), 0x6c, val);
+ pci_clear32(NODE_HT(node), 0x6c, ((1 << 1) | (1 << 0)));
print_spew(" done.\n");
}
--- src/northbridge/amd/amdk8/exit_from_self.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-fcca79-exit_from_self.c 2010-10-05 03:02:28.248444280 +0200
@@ -75,12 +75,7 @@ void exit_from_self(int controllers, con
printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
if (is_post_rev_g) {
- dcl =
- pci_read_config32(ctrl[i].f2,
- DRAM_TIMING_HIGH);
- dcl |= (1 << 18);
- pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
- dcl);
+ pci_set32(ctrl[i].f2, DRAM_TIMING_HIGH, (1 << 18));
}
dcl = DI_EnDramInit;
@@ -90,17 +85,10 @@ void exit_from_self(int controllers, con
printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
- dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
- dcl &= ~DI_EnDramInit;
- pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
+ pci_clear32(ctrl[i].f2, DRAM_INIT, DI_EnDramInit);
if (is_post_rev_g) {
- dcl =
- pci_read_config32(ctrl[i].f2,
- DRAM_TIMING_HIGH);
- dcl &= ~(1 << 18);
- pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
- dcl);
+ pci_clear32(ctrl[i].f2, DRAM_TIMING_HIGH, (1 << 18));
}
dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP);
--- src/northbridge/amd/amdk8/misc_control.c 2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-2e0206-misc_control.c 2010-10-05 03:02:28.568443933 +0200
@@ -118,22 +118,15 @@ static void misc_control_init(struct dev
/* Disable Machine checks from Invalid Locations.
* This is needed for PC backwards compatibility.
*/
- cmd = pci_read_config32(dev, 0x44);
- cmd |= (1<<6) | (1<<25);
- pci_write_config32(dev, 0x44, cmd );
+ pci_set32(dev, 0x44, (1 << 6) | (1 << 25));
#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 58
* Disable CPU low power states C2, C1 and throttling
*/
- cmd = pci_read_config32(dev, 0x80);
- cmd &= ~(1<<0);
- pci_write_config32(dev, 0x80, cmd );
- cmd = pci_read_config32(dev, 0x84);
- cmd &= ~(1<<24);
- cmd &= ~(1<<8);
- pci_write_config32(dev, 0x84, cmd );
+ pci_clear32(dev, 0x80, (1 << 0));
+ pci_clear32(dev, 0x84, ((1 << 24) | (1 << 8)));
/* Errata 66
* Limit the number of downstream posted requests to 1
--- src/northbridge/amd/amdfam10/reset_test.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-6362c6-reset_test.c 2010-10-05 03:02:28.920445071 +0200
@@ -95,9 +95,7 @@ static void set_bios_reset(void)
for(i = 0; i < nodes; i++) {
dev = NODE_PCI(i,0);
- htic = pci_read_config32(dev, HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ pci_clear32(dev, HT_INIT_CONTROL, HTIC_BIOSR_Detect);
}
}
--- src/northbridge/amd/amdfam10/misc_control.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-52a7ca-misc_control.c 2010-10-05 03:02:29.236444958 +0200
@@ -130,9 +130,7 @@ static void misc_control_init(struct dev
/* Disable Machine checks from Invalid Locations.
* This is needed for PC backwards compatibility.
*/
- cmd = pci_read_config32(dev, 0x44);
- cmd |= (1<<6) | (1<<25);
- pci_write_config32(dev, 0x44, cmd );
+ pci_set32(dev, 0x44, (1 << 6) | (1 << 25));
printk(BIOS_DEBUG, "done.\n");
}
--- src/northbridge/via/cn400/agp.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-673e7f-agp.c 2010-10-05 03:02:29.504446503 +0200
@@ -87,9 +87,7 @@ static void agp_init(device_t dev)
pci_write_config8(dev, 0xc2, 0x40);
/* Enable CPU/PMSTR GART Access and DBI function. */
- reg32 = pci_read_config8(dev, 0xbf);
- reg32 |= 0x8c;
- pci_write_config8(dev, 0xbf, reg32);
+ pci_set8(dev, 0xbf, 0x8c);
/* Enable AGP Aperture. */
pci_write_config32(dev, 0x90, 0x0180);
--- src/northbridge/via/cn400/raminit.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-99fde2-raminit.c 2010-10-05 03:02:29.856443993 +0200
@@ -137,9 +137,7 @@ static void c3_cpu_setup(device_t dev)
pci_write_config8(dev, 0x57, 0x69);
/* CPU Host Bus Final Setup */
- reg8 = pci_read_config8(dev, 0x54);
- reg8 |= 0x08;
- pci_write_config8(dev, 0x54, reg8);
+ pci_set8(dev, 0x54, 0x08);
}
@@ -550,9 +548,7 @@ static void ddr_ram_setup(void)
Don't change Frequency from power up defaults
This seems to lockup the RAM interface
*/
- c = pci_read_config8(ctrl.d0f2, 0x54);
- c |= 0x10;
- pci_write_config8(ctrl.d0f2, 0x54, c);
+ pci_set8(ctrl.d0f2, 0x54, 0x10);
i = 0x008; // Used later to set SDRAM MSR
}
--- src/northbridge/via/cn400/northbridge.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-41cea7-northbridge.c 2010-10-05 03:02:30.632444027 +0200
@@ -92,22 +92,16 @@ static void memctrl_init(device_t dev)
pci_write_config8(dev, 0x81, paged);
pci_write_config8(dev, 0x83, pagee);
/* PAGE F are read/writable */
- shadowreg = pci_read_config8(dev, 0x82);
- shadowreg |= pagef;
- pci_write_config8(dev, 0x82, shadowreg);
+ pci_set8(dev, 0x82, pagef);
pci_write_config8(vlink_dev, 0x61, pagec);
pci_write_config8(vlink_dev, 0x62, paged);
pci_write_config8(vlink_dev, 0x64, pagee);
- shadowreg = pci_read_config8(vlink_dev, 0x63);
- shadowreg |= pagef;
- pci_write_config8(vlink_dev, 0x63, shadowreg);
+ pci_set8(vlink_dev, 0x63, pagef);
/* Activate VGA Frame Buffer */
- reg8 = pci_read_config8(dev, 0xA0);
- reg8 |= 0x01;
- pci_write_config8(dev, 0xA0, reg8);
+ pci_set8(dev, 0xA0, 0x01);
#ifdef DEBUG_CN400
printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
--- src/northbridge/via/cn400/vlink.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-f98929-vlink.c 2010-10-05 03:02:31.132443968 +0200
@@ -46,9 +46,7 @@ static void vlink_init(device_t dev)
printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
/* Disconnect the VLink Before Changing Settings */
- reg = pci_read_config8(dev, 0x47);
- reg |= 0x04;
- pci_write_config8(dev, 0x47, reg);
+ pci_set8(dev, 0x47, 0x04);
/* Wait for anything pending to flush */
noop_1k(20);
@@ -85,27 +83,21 @@ static void vlink_init(device_t dev)
/* V-Link NB Compensation Control */
pci_write_config8(dev, 0xB5, 0x46);
pci_write_config8(dev, 0xB6, 0x68);
- reg = pci_read_config8(dev, 0xB4);
- reg |= 0x01;
- pci_write_config8(dev, 0xB4, reg);
+ pci_set8(dev, 0xB4, 0x01);
/* V-Link NB Receive Strobe Delay */
pci_write_config8(dev, 0xB7, 0x02);
/* V-Link SB Compensation Control */
pci_write_config8(dev, 0xB9, 0x84);
- reg = pci_read_config8(dev, 0xB8);
- reg |= 0x01;
- pci_write_config8(dev, 0xB8, reg);
+ pci_set8(dev, 0xB8, 0x01);
pci_write_config8(dev, 0xBA, 0x6a);
pci_write_config8(dev, 0xBB, 0x01);
#ifdef DEBUG_CN400
/* Reconnect the VLink Before Continuing*/
- reg = pci_read_config8(dev, 0x47);
- reg &= ~0x04;
- pci_write_config8(dev, 0x47, reg);
+ pci_clear8(dev, 0x47, 0x04);
printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
--- src/northbridge/via/cn700/agp.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-2b9eca-agp.c 2010-10-05 03:02:31.588443867 +0200
@@ -76,9 +76,7 @@ static void agp_init(device_t dev)
pci_write_config32(dev, 0x10, 0xf8000008);
/* Enable CPU/PMSTR GART Access. */
- reg32 = pci_read_config8(dev, 0xbf);
- reg32 |= 0x80;
- pci_write_config8(dev, 0xbf, reg32);
+ pci_set8(dev, 0xbf, 0x80);
/* Enable AGP Aperture. */
reg32 = pci_read_config32(dev, 0x94);
--- src/northbridge/via/cn700/northbridge.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-4d0cbc-northbridge.c 2010-10-05 03:02:31.940443851 +0200
@@ -69,9 +69,7 @@ static void memctrl_init(device_t dev)
pci_write_config8(dev, 0x81, paged);
pci_write_config8(dev, 0x82, pagee);
/* PAGE F are read/writable */
- shadowreg = pci_read_config8(dev, 0x83);
- shadowreg |= pagef;
- pci_write_config8(dev, 0x83, shadowreg);
+ pci_set8(dev, 0x83, pagef);
/* vlink mirror */
vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
@@ -80,9 +78,7 @@ static void memctrl_init(device_t dev)
pci_write_config8(vlink_dev, 0x62, paged);
pci_write_config8(vlink_dev, 0x64, pagee);
- shadowreg = pci_read_config8(vlink_dev, 0x63);
- shadowreg |= pagef;
- pci_write_config8(vlink_dev, 0x63, shadowreg);
+ pci_set8(vlink_dev, 0x63, pagef);
}
}
--- src/northbridge/via/cx700/cx700_sata.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-c55eec-cx700_sata.c 2010-10-05 03:02:32.400443929 +0200
@@ -77,9 +77,7 @@ static void sata_init(struct device *dev
pci_write_config8(dev, 0x6b, reg8);
/* Enable EIDE (secondary channel) even if SATA disabled */
- reg8 = pci_read_config8(dev, 0xc0);
- reg8 |= 0x1;
- pci_write_config8(dev, 0xc0, reg8);
+ pci_set8(dev, 0xc0, 0x1);
// Enable bus mastering, memory space acces, io space access
pci_write_config16(dev, 0x04, 0x0007);
@@ -95,9 +93,7 @@ static void sata_init(struct device *dev
pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
/* Enable read/write prefetch buffers */
- reg8 = pci_read_config8(dev, 0xc1);
- reg8 |= 0x30;
- pci_write_config8(dev, 0xc1, reg8);
+ pci_set8(dev, 0xc1, 0x30);
/* Set FIFO thresholds like */
pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */
@@ -111,16 +107,12 @@ static void sata_init(struct device *dev
pci_write_config8(dev, 0x46, 0x8);
/* EIDE Configuration */
- reg8 = pci_read_config8(dev, 0xc4);
- reg8 |= 0x10;
- pci_write_config8(dev, 0xc4, reg8);
+ pci_set8(dev, 0xc4, 0x10);
pci_write_config8(dev, 0xc5, 0xc);
/* Interrupt Line */
- reg8 = pci_read_config8(dev, 0x45);
- reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */
- pci_write_config8(dev, 0x45, reg8);
+ pci_clear8(dev, 0x45, (1 << 4));
pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */
@@ -128,9 +120,7 @@ static void sata_init(struct device *dev
pci_write_config16(dev, 0x48, 0x5d5d);
/* Enable only compatibility mode. */
- reg8 = pci_read_config8(dev, 0x42);
- reg8 &= ~0xa0;
- pci_write_config8(dev, 0x42, reg8);
+ pci_clear8(dev, 0x42, 0xa0);
reg8 = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
--- src/northbridge/via/cx700/raminit.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-fc4080-raminit.c 2010-10-05 03:02:32.788443855 +0200
@@ -456,9 +456,7 @@ static void sdram_set_safe_values(const
* This is a necessary sequence.
*/
udelay(2000);
- regs = pci_read_config8(MEMCTRL, 0x90);
- regs |= 0x7;
- pci_write_config8(MEMCTRL, 0x90, regs);
+ pci_set8(MEMCTRL, 0x90, 0x7);
udelay(2000);
regs = pci_read_config8(MEMCTRL, 0x90);
regs &= ~0x7;
@@ -475,9 +473,7 @@ static void sdram_set_safe_values(const
udelay(1);
regs &= ~0xc0;
pci_write_config8(MEMCTRL, 0x6b, regs);
- regs = pci_read_config8(MEMCTRL, 0x6f);
- regs |= 0x1;
- pci_write_config8(MEMCTRL, 0x6f, regs);
+ pci_set8(MEMCTRL, 0x6f, 0x1);
/**********************************************/
/* Set DRAM Timing Setting (DDR2 533) */
@@ -671,9 +667,7 @@ static void sdram_set_safe_values(const
pci_write_config8(HOSTCTRL, Host_Reg_Val[val], Host_Reg_Val[val + 1]);
/* F2_RX51[7]=0, disable DRDY timing */
- regs = pci_read_config8(HOSTCTRL, 0x51);
- regs &= ~0x80;
- pci_write_config8(HOSTCTRL, 0x51, regs);
+ pci_clear8(HOSTCTRL, 0x51, 0x80);
/**********************************************/
/* Set DRAM BurstLength */
@@ -899,9 +893,7 @@ static void sdram_set_safe_values(const
val |= t;
pci_write_config8(HOSTCTRL, 0x57, val);
- regs = pci_read_config8(HOSTCTRL, 0x51);
- regs |= t;
- pci_write_config8(HOSTCTRL, 0x51, regs);
+ pci_set8(HOSTCTRL, 0x51, t);
regs = pci_read_config8(MEMCTRL, 0x90);
regs &= 0x7;
@@ -913,9 +905,7 @@ static void sdram_set_safe_values(const
regs |= val;
pci_write_config8(MEMCTRL, 0x76, regs);
- regs = pci_read_config8(MEMCTRL, 0x6f);
- regs |= 0x10;
- pci_write_config8(MEMCTRL, 0x6f, regs);
+ pci_set8(MEMCTRL, 0x6f, 0x10);
/***************************************************/
/* Find suitable DQS value for ChA and ChB */
@@ -983,9 +973,7 @@ static void step_2_19(const struct mem_c
u8 val;
// Step 2
- val = pci_read_config8(MEMCTRL, 0x69);
- val &= ~0x03;
- pci_write_config8(MEMCTRL, 0x69, val);
+ pci_clear8(MEMCTRL, 0x69, 0x03);
/* Step 3 Apply NOP. */
print_spew("RAM Enable 1: Apply NOP\n");
@@ -1445,9 +1433,7 @@ static void sdram_enable(const struct me
reg8 &= 0x11;
pci_write_config8(MEMCTRL, 0x50, reg8);
pci_write_config8(MEMCTRL, 0x51, reg8);
- reg8 = pci_read_config8(MEMCTRL, 0x6b);
- reg8 &= ~0x08;
- pci_write_config8(MEMCTRL, 0x6b, reg8);
+ pci_clear8(MEMCTRL, 0x6b, 0x08);
/****************************************************************/
/* DRAM re-initialize for burst length */
@@ -1474,9 +1460,7 @@ static void sdram_enable(const struct me
reg8 &= 0x11;
pci_write_config8(MEMCTRL, 0x51, reg8);
- reg8 = pci_read_config8(MEMCTRL, 0x6b);
- reg8 &= ~0x08;
- pci_write_config8(MEMCTRL, 0x6b, reg8);
+ pci_clear8(MEMCTRL, 0x6b, 0x08);
for (i = 0; i < 4; i += 2) {
reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
@@ -1609,13 +1593,9 @@ static void sdram_enable(const struct me
outl(0x80000188, 0xcf8);
outb(0xcf, 0xcfc);
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xa5);
- reg8 |= 0x10;
- pci_write_config8(PCI_DEV(0, 0, 0), 0xa5, reg8);
+ pci_set8(PCI_DEV(0, 0, 0), 0xa5, 0x10);
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0x91);
- reg8 |= 0x20;
- pci_write_config8(PCI_DEV(0, 0, 0), 0x91, reg8);
+ pci_set8(PCI_DEV(0, 0, 0), 0x91, 0x20);
#endif
static const struct regmask {
--- src/northbridge/via/cx700/cx700_agp.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-a74494-cx700_agp.c 2010-10-05 03:02:35.760445670 +0200
@@ -36,18 +36,14 @@ static void agp_bridge_init(device_t dev
pci_write_config8(north_dev, 0xa2, 0x4a);
- reg8 = pci_read_config8(north_dev, 0xc0);
- reg8 |= 0x1;
- pci_write_config8(north_dev, 0xc0, reg8);
+ pci_set8(north_dev, 0xc0, 0x1);
/*
* Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
* We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
*/
north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
- reg8 = pci_read_config8(north_dev, 0xb5);
- reg8 |= 0x3;
- pci_write_config8(north_dev, 0xb5, reg8);
+ pci_set8(north_dev, 0xb5, 0x3);
pci_write_config8(north_dev, 0x94, 0x20);
pci_write_config8(north_dev, 0x13, 0xd0);
--- src/northbridge/via/cx700/cx700_lpc.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-d9291b-cx700_lpc.c 2010-10-05 03:02:36.060447035 +0200
@@ -172,9 +172,7 @@ static void cx700_set_lpc_registers(stru
printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
// enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
+ pci_set8(dev, 0x6C, 0x80);
// Map 4MB of FLASH into the address space
// pci_write_config8(dev, 0x41, 0x7f);
@@ -182,14 +180,10 @@ static void cx700_set_lpc_registers(stru
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x44;
- pci_write_config8(dev, 0x40, enables);
+ pci_set8(dev, 0x40, 0x44);
/* DMA Line buffer control */
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
+ pci_set8(dev, 0x42, 0xf0);
/* I/O recovery time */
pci_write_config8(dev, 0x4c, 0x44);
@@ -204,17 +198,11 @@ static void cx700_set_lpc_registers(stru
pci_write_config8(dev, 0x48, 0x0c);
/* Set SM Misc Control: Enable Internal APIC . */
- enables = pci_read_config8(dev, 0x58);
- enables |= 1 << 6;
- pci_write_config8(dev, 0x58, enables);
- enables = pci_read_config8(dev, 0x4d);
- enables |= 1 << 3;
- pci_write_config8(dev, 0x4d, enables);
+ pci_set8(dev, 0x58, 1 << 6);
+ pci_set8(dev, 0x4d, 1 << 3);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
/* enable KBC configuration */
pci_write_config8(dev, 0x51, 0x1f);
--- src/northbridge/via/cx700/cx700_usb.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-254bad-cx700_usb.c 2010-10-05 03:02:36.544451651 +0200
@@ -33,9 +33,7 @@ static void usb_init(struct device *dev)
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
- reg8 = pci_read_config8(dev, 0xca);
- reg8 |= (1 << 0);
- pci_write_config8(dev, 0xca, reg8);
+ pci_set8(dev, 0xca, (1 << 0));
printk(BIOS_DEBUG, "done.\n");
}
--- src/northbridge/via/vx800/driving_setting.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-853091-driving_setting.c 2010-10-05 03:02:36.769444168 +0200
@@ -218,9 +218,7 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr
Data |= 0x30;
pci_write_config8(MEMCTRL, 0xD4, Data);
- Data = pci_read_config8(MEMCTRL, 0x9e);
- Data |= 0x01;
- pci_write_config8(MEMCTRL, 0x9e, Data);
+ pci_set8(MEMCTRL, 0x9e, 0x01);
}
}
@@ -261,14 +259,10 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr
pci_write_config8(MEMCTRL, 0xD4, Data);
//enable CHB differential DQS input
- Data = pci_read_config8(MEMCTRL, 0x9E);
- Data |= 0x02;
- pci_write_config8(MEMCTRL, 0x9E, Data);
+ pci_set8(MEMCTRL, 0x9E, 0x02);
}
//enable ODT Control
- Data = pci_read_config8(MEMCTRL, 0x9e);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0x9e, Data);
+ pci_set8(MEMCTRL, 0x9e, 0x80);
}
void DrivingDQS(DRAM_SYS_ATTR * DramAttr)
--- src/northbridge/via/vx800/uma_ram_setting.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-cf52e9-uma_ram_setting.c 2010-10-05 03:02:37.265443981 +0200
@@ -81,9 +81,7 @@ void SetUMARam(void)
SLD1F0Val = 0;
VgaPortVal = 0;
- ByteVal = pci_read_config8(MEMCTRL, 0xa1);
- ByteVal |= 0x80;
- pci_write_config8(MEMCTRL, 0xa1, ByteVal);
+ pci_set8(MEMCTRL, 0xa1, 0x80);
//set VGA Timer
pci_write_config8(MEMCTRL, 0xa2, 0xee);
@@ -179,15 +177,10 @@ void SetUMARam(void)
pci_write_config8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
//enable GFx memory space access control for S.L and mmio
- ByteVal = pci_read_config8(d0f0_dev, 0xD4);
- ByteVal |= 0x03;
- //ByteVal |= 0x01;
- pci_write_config8(d0f0_dev, 0xD4, ByteVal);
+ pci_set8(d0f0_dev, 0xD4, 0x03);
//enable Base VGA 16 Bits Decode
- ByteVal = pci_read_config8(d0f0_dev, 0xfe);
- ByteVal |= 0x10;
- pci_write_config8(d0f0_dev, 0xfe, ByteVal);
+ pci_set8(d0f0_dev, 0xfe, 0x10);
//disable CHB L.L
//set VGA memory selection
--- src/northbridge/via/vx800/examples/romstage.c 2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-cf82b2-romstage.c 2010-10-05 03:02:38.057447117 +0200
@@ -98,9 +98,7 @@ static void enable_shadow_ram(void)
uint8_t shadowreg;
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
/* 0xf0000-0xfffff - ACPI tables */
- shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
- shadowreg |= 0x30;
- pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+ pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
/* 0xe0000-0xeffff - elfload? */
pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
--- src/northbridge/via/vx800/dev_init.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-b972cf-dev_init.c 2010-10-05 03:02:38.677443869 +0200
@@ -360,9 +360,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr
/* Step 2 */
/* Disable bank paging and multi page. */
- Data = pci_read_config8(MEMCTRL, 0x69);
- Data &= ~0x03;
- pci_write_config8(MEMCTRL, 0x69, Data);
+ pci_clear8(MEMCTRL, 0x69, 0x03);
Reg6BVal = pci_read_config8(MEMCTRL, 0x6b);
Reg6BVal &= ~0x07;
@@ -515,9 +513,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0x6b, Data);
/* Enable bank paging and multi page. */
- Data = pci_read_config8(MEMCTRL, 0x69);
- Data |= 0x03;
- pci_write_config8(MEMCTRL, 0x69, Data);
+ pci_set8(MEMCTRL, 0x69, 0x03);
}
/*===================================================================
@@ -900,9 +896,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
* Step 4. Enable the initialization mode of DRAM Controller C with
* NB's PLL clock.
*/
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x60;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x60);
/* Step 5. NOP command enable. */
Data = pci_read_config8(MEMCTRL, 0xdb);
@@ -911,9 +905,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xdb, Data);
/* Step 6. Issue a nop cycle, RegDB[1] 0 -> 1. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -940,9 +932,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
/* step 9. Issue a precharge all cycle, RegD3[7] 0 -> 1. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -960,9 +950,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Step 12. Issue EMRS cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -980,9 +968,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Step 15. Issue MRS cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1000,9 +986,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Step 17. Issue precharge all cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1022,9 +1006,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
//repeat issue 8 CBR cycle, between each cycle stop 100us
for (Idx = 0; Idx < 8; Idx++) {
// issue CBR cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
WaitMicroSec(100);
@@ -1059,9 +1041,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
//step 24. issue MRS cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1079,9 +1059,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
//step 27. issue EMRS cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1093,9 +1071,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
pci_write_config8(MEMCTRL, 0xf9, Data);
//step 29. issue EMRS cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1141,9 +1117,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Issue active cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1161,9 +1135,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Issue read/completion cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1181,9 +1153,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Issue write cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1201,9 +1171,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Issue read/completion cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1221,9 +1189,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
// issue active cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1241,9 +1207,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
// issue read/completion cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1261,9 +1225,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
// issue read cycle
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
@@ -1281,9 +1243,7 @@ CB_STATUS VerifyChc(void)
pci_write_config8(MEMCTRL, 0xf9, Data);
/* Issue read/completion cycle. */
- Data = pci_read_config8(MEMCTRL, 0xdb);
- Data |= 0x2;
- pci_write_config8(MEMCTRL, 0xdb, Data);
+ pci_set8(MEMCTRL, 0xdb, 0x2);
Data &= 0xFD;
pci_write_config8(MEMCTRL, 0xdb, Data);
--- src/northbridge/via/vx800/rank_map.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-86195f-rank_map.c 2010-10-05 03:02:39.729452751 +0200
@@ -172,9 +172,7 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR *
//must set BA2 enable if any 8-bank device exists
if (HasThreeBitBA) {
- Data = pci_read_config8(MEMCTRL, 0x53);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0x53, Data);
+ pci_set8(MEMCTRL, 0x53, 0x80);
}
#if 1
for (RankIndex = 0; DramAttr->RankSize[RankIndex] != 0; RankIndex++) {
@@ -213,9 +211,7 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * D
Data &= 0x1;
pci_write_config8(MEMCTRL, 0x50, Data);
// disable MA32/16 MA33/17 swap in memory init it has this Reg fill
- Data = pci_read_config8(MEMCTRL, 0x6b);
- Data &= ~0x08;
- pci_write_config8(MEMCTRL, 0x6b, Data);
+ pci_clear8(MEMCTRL, 0x6b, 0x08);
Data = 0x00;
for (SlotNum = 0; SlotNum < MAX_DIMMS; SlotNum++) {
--- src/northbridge/via/vx800/vx800_lpc.c 2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-d93d22-vx800_lpc.c 2010-10-05 03:02:40.273459181 +0200
@@ -201,9 +201,7 @@ static void setup_pm(device_t dev)
static void S3_ps2_kb_ms_wakeup(struct device *dev)
{
u8 enables;
- enables = pci_read_config8(dev, 0x51);
- enables |= 2;
- pci_write_config8(dev, 0x51, enables);
+ pci_set8(dev, 0x51, 2);
outb(0xe0, 0x2e);
outb(0x0b, 0x2f); //if 09,then only support kb wakeup
@@ -238,9 +236,7 @@ static void vx800_sb_init(struct device
unsigned char enables;
// enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
+ pci_set8(dev, 0x6C, 0x80);
// Map 4MB of FLASH into the address space
// pci_write_config8(dev, 0x41, 0x7f);
@@ -248,14 +244,10 @@ static void vx800_sb_init(struct device
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x44;
- pci_write_config8(dev, 0x40, enables);
+ pci_set8(dev, 0x40, 0x44);
/* DMA Line buffer control */
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
+ pci_set8(dev, 0x42, 0xf0);
/* I/O recovery time */
pci_write_config8(dev, 0x4c, 0x44);
@@ -265,23 +257,17 @@ static void vx800_sb_init(struct device
/* Set 0x5b to 0x01 to match Award */
//pci_write_config8(dev, 0x5b, 0x01);
- enables = pci_read_config8(dev, 0x5b);
- enables |= 0x01;
- pci_write_config8(dev, 0x5b, enables);
+ pci_set8(dev, 0x5b, 0x01);
/* Set Read Pass Write Control Enable */
pci_write_config8(dev, 0x48, 0x0c);
/* Set 0x58 to 0x42 APIC and RTC. */
//pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
- enables = pci_read_config8(dev, 0x58);
- enables |= 0x41; //
- pci_write_config8(dev, 0x58, enables);
+ pci_set8(dev, 0x58, 0x41);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
/* enable serial irq */
pci_write_config8(dev, 0x52, 0x9);
--- src/northbridge/intel/i855/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-31e198-raminit.c 2010-10-05 03:02:40.760444095 +0200
@@ -406,9 +406,7 @@ static void set_initialize_complete(cons
{
uint32_t drc_reg;
- drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);
- drc_reg |= (1 << 29);
- pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
+ pci_set32(NORTHBRIDGE_MMC, DRC, (1 << 29));
}
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
--- src/northbridge/intel/i945/early_init.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-4c8699-early_init.c 2010-10-05 03:02:41.736443862 +0200
@@ -516,9 +516,7 @@ static void i945_setup_pci_express_x16(v
printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
- reg16 |= DEVEN_D1F0;
- pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
+ pci_set16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208);
reg32 &= ~(1 << 8);
@@ -530,13 +528,9 @@ static void i945_setup_pci_express_x16(v
*/
/* First we reset the secondary bus */
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
- reg16 |= (1 << 6); /* SRESET */
- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+ pci_set16(PCI_DEV(0, 0x01, 0), 0x3e, (1 << 6));
/* Read back and clear reset bit. */
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
- reg16 &= ~(1 << 6); /* SRESET */
- pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+ pci_clear16(PCI_DEV(0, 0x01, 0), 0x3e, (1 << 6));
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
@@ -641,14 +635,10 @@ static void i945_setup_pci_express_x16(v
pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
/* DEVEN */
- reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54);
- reg32 &= ~((1 << 3) | (1 << 4));
- pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32);
+ pci_clear32(PCI_DEV(0, 0x0, 0), 0x54, ((1 << 3) | (1 << 4)));
/* Set VGA enable bit in PCIe bridge */
- reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e);
- reg16 |= (1 << 3);
- pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16);
+ pci_set16(PCI_DEV(0, 0x1, 0), 0x3e, (1 << 3));
}
/* Enable GPEs */
@@ -785,9 +775,7 @@ disable_pciexpress_x16_link:
printk(BIOS_DEBUG, "ok\n");
/* Finally: Disable the PCI config header */
- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
- reg16 &= ~DEVEN_D1F0;
- pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
+ pci_clear16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
}
static void i945_setup_root_complex_topology(void)
--- src/northbridge/intel/i945/raminit.c 2010-10-01 11:41:29.000000000 +0200
+++ /tmp/cocci-output-5159-515b3c-raminit.c 2010-10-05 03:02:43.012443829 +0200
@@ -254,9 +254,7 @@ static void sdram_detect_errors(struct s
}
/* Set SLP_S3# Assertion Stretch Enable */
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
- reg8 |= (1 << 3);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 3));
if (do_reset) {
printk(BIOS_DEBUG, "Reset required.\n");
@@ -267,9 +265,7 @@ static void sdram_detect_errors(struct s
}
/* Set DRAM initialization bit in ICH7 */
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
- reg8 |= (1<<7);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
/* clear self refresh if not wake-up from suspend */
if (sysinfo->boot_path != 2) {
@@ -2056,10 +2052,7 @@ static void sdram_program_graphics_frequ
}
pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
- reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
-
- reg8 |= (1<<3) | (1<<1);
- pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+ pci_set8(PCI_DEV(0, 2, 0), GCFC + 1, (1 << 3) | (1 << 1));
reg8 |= 0x0f;
pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
@@ -2112,9 +2105,7 @@ static void sdram_program_memory_frequen
*/
goto cache_code;
vco_update:
- reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
- reg8 &= ~(1 << 7);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
clkcfg &= ~(1 << 10);
MCHBAR32(CLKCFG) = clkcfg;
@@ -2581,13 +2572,9 @@ static void sdram_power_management(struc
MCHBAR32(FSBPMC4) |= (1 << 4);
}
- reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
- reg8 |= (1 << 4);
- pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
-
- reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
- reg8 |= (1 << 2);
- pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
+ pci_set8(PCI_DEV(0, 0x0, 0), 0xfc, (1 << 4));
+
+ pci_set8(PCI_DEV(0, 0x2, 0), 0xc1, (1 << 2));
#ifdef C2_SELF_REFRESH_DISABLE
@@ -3147,9 +3134,7 @@ void sdram_initialize(int boot_path)
sdram_enable_rcomp();
/* Tell ICH7 that we're done */
- reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
- reg8 &= ~(1 << 7);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
printk(BIOS_DEBUG, "RAM initialization finished.\n");
--- src/northbridge/intel/e7501/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-7507a1-raminit.c 2010-10-05 03:02:47.444443983 +0200
@@ -1449,9 +1449,7 @@ static void configure_e7501_cas_latency(
pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
/* set master DLL reset */
- dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
- dword |= (1 << 26);
- pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+ pci_set32(PCI_DEV(0, 0, 0), 0x88, (1 << 26));
dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */
dword |= 0xd2109800;
@@ -1461,9 +1459,7 @@ static void configure_e7501_cas_latency(
pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
maybe_dram_read_timing);
- dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */
- dword &= ~(1 << 26);
- pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+ pci_clear32(PCI_DEV(0, 0, 0), 0x88, (1 << 26));
return;
@@ -1674,13 +1670,9 @@ static void enable_e7501_clocks(uint8_t
static void RAM_RESET_DDR_PTR(void)
{
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
- byte |= (1 << 4);
- pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
-
- byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
- byte &= ~(1 << 4);
- pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
+ pci_set8(PCI_DEV(0, 0, 0), 0x88, (1 << 4));
+
+ pci_clear8(PCI_DEV(0, 0, 0), 0x88, (1 << 4));
}
//----------------------------------------------------------------------------------
@@ -1762,9 +1754,7 @@ static void ram_set_rcomp_regs(void)
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/*enable access to the rcomp bar */
- dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
- dword |= (1 << 22);
- pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
+ pci_set32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, (1 << 22));
// Set the RCOMP MMIO base address
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
@@ -1851,9 +1841,7 @@ static void ram_set_rcomp_regs(void)
SLOW_DOWN_IO;
/*disable access to the rcomp bar */
- dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
- dword &= ~(1 << 22);
- pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
+ pci_clear32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, (1 << 22));
}
@@ -1961,15 +1949,11 @@ static void sdram_enable(int controllers
configure_e7501_ram_addresses(ctrl, dimm_mask);
/* Finally enable refresh */
- dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
- dram_controller_mode |= (1 << 29);
- pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+ pci_set32(PCI_DEV(0, 0, 0), DRC, (1 << 29));
EXTRA_DELAY;
initialize_ecc();
- dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
- dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit
- pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+ pci_set32(PCI_DEV(0, 0, 0), DRC, (1 << 17));
RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
--- src/northbridge/intel/e7520/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-017572-raminit.c 2010-10-05 03:02:49.172443879 +0200
@@ -1326,9 +1326,7 @@ static void sdram_enable(int controllers
}
/* Bring memory subsystem on line */
- data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
- data32 |= (1 << 31);
- pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
+ pci_set32(PCI_DEV(0, 0x00, 0), 0x98, (1 << 31));
/* wait for completion */
print_debug("Waiting for mem complete\n");
while(1) {
--- src/northbridge/intel/e7525/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-0ecb7a-raminit.c 2010-10-05 03:02:50.880443887 +0200
@@ -1293,9 +1293,7 @@ static void sdram_enable(int controllers
}
/* Bring memory subsystem on line */
- data32 = pci_read_config32(ctrl->f0, 0x98);
- data32 |= (1 << 31);
- pci_write_config32(ctrl->f0, 0x98, data32);
+ pci_set32(ctrl->f0, 0x98, (1 << 31));
/* wait for completion */
print_debug("Waiting for mem complete\n");
while(1) {
--- src/northbridge/intel/i3100/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-90d064-raminit.c 2010-10-05 03:02:52.688451877 +0200
@@ -1183,9 +1183,7 @@ static void sdram_enable(int controllers
}
/* Bring memory subsystem on line */
- data32 = pci_read_config32(ctrl->f0, 0x98);
- data32 |= (1 << 31);
- pci_write_config32(ctrl->f0, 0x98, data32);
+ pci_set32(ctrl->f0, 0x98, (1 << 31));
/* wait for completion */
print_debug("Waiting for mem complete\n");
while(1) {
--- src/northbridge/intel/i82830/raminit.c 2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-b68265-raminit.c 2010-10-05 03:02:54.684453048 +0200
@@ -471,10 +471,7 @@ static void northbridge_set_registers(vo
igd_memory = 0x0;
}
- value = pci_read_config16(NORTHBRIDGE, GCC1);
- value |= igd_memory << 4;
- value |= 1; // 64MB aperture
- pci_write_config16(NORTHBRIDGE, GCC1, value);
+ pci_set16(NORTHBRIDGE, GCC1, igd_memory << 4 | 1);
printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
}
@@ -494,15 +491,11 @@ static void sdram_initialize(void)
/* Enable Refresh */
PRINTK_DEBUG("Enabling Refresh\n");
- reg32 = pci_read_config32(NORTHBRIDGE, DRC);
- reg32 |= (RAM_COMMAND_REFRESH << 8);
- pci_write_config32(NORTHBRIDGE, DRC, reg32);
+ pci_set32(NORTHBRIDGE, DRC, (RAM_COMMAND_REFRESH << 8));
/* Set initialization complete */
PRINTK_DEBUG("Setting initialization complete\n");
- reg32 = pci_read_config32(NORTHBRIDGE, DRC);
- reg32 |= (RAM_COMMAND_IC << 29);
- pci_write_config32(NORTHBRIDGE, DRC, reg32);
+ pci_set32(NORTHBRIDGE, DRC, (RAM_COMMAND_IC << 29));
/* Setup Initial Northbridge Registers */
northbridge_set_registers();
--- src/southbridge/ti/pci7420/pci7420_cardbus.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-174a81-pci7420_cardbus.c 2010-10-05 03:02:55.325444094 +0200
@@ -49,14 +49,10 @@ static void pci7420_cardbus_init(device_
smartcard_enabled = config->smartcard_enabled;
}
- reg32 = pci_read_config32(dev, SYSCTL);
- reg32 |= RIMUX;
- pci_write_config32(dev, SYSCTL, reg32);
+ pci_set32(dev, SYSCTL, RIMUX);
/* Enable SPKROUT */
- reg8 = pci_read_config8(dev, CARDCTL);
- reg8 |= SPKROUTEN;
- pci_write_config8(dev, CARDCTL, reg8);
+ pci_set8(dev, CARDCTL, SPKROUTEN);
/* Power switch select and FM disable */
reg16 = pci_read_config16(dev, GENCTL);
--- src/southbridge/amd/sb600/sb600_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-040714-sb600_ide.c 2010-10-05 03:02:55.765445227 +0200
@@ -31,20 +31,14 @@ static void ide_init(struct device *dev)
u8 byte;
/* RPR10.1 disable MSI */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1 << 16);
- pci_write_config32(dev, 0x70, dword);
+ pci_clear32(dev, 0x70, (1 << 16));
/* Ultra DMA mode */
/* enable UDMA */
- byte = pci_read_config8(dev, 0x54);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x54, byte);
+ pci_set8(dev, 0x54, 1 << 0);
/* Enable I/O Access&& Bus Master */
- dword = pci_read_config16(dev, 0x4);
- dword |= 1 << 2;
- pci_write_config16(dev, 0x4, dword);
+ pci_set16(dev, 0x4, 1 << 2);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
--- src/southbridge/amd/sb600/sb600_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1edd52-sb600_lpc.c 2010-10-05 03:02:56.049445413 +0200
@@ -37,27 +37,19 @@ static void lpc_init(device_t dev)
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword = pci_read_config32(sm_dev, 0x64);
- dword |= 1 << 20;
- pci_write_config32(sm_dev, 0x64, dword);
+ pci_set32(sm_dev, 0x64, 1 << 20);
/* Initialize isa dma */
isa_dma_init();
/* RPR 7.2 Enable DMA transaction on the LPC bus */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* RPR 7.3 Disable the timeout mechanism on LPC */
- byte = pci_read_config8(dev, 0x48);
- byte &= ~(1 << 7);
- pci_write_config8(dev, 0x48, byte);
+ pci_clear8(dev, 0x48, (1 << 7));
/* RPR 7.5 Disable LPC MSI Capability */
- byte = pci_read_config8(dev, 0x78);
- byte &= ~(1 << 1);
- pci_write_config8(dev, 0x78, byte);
+ pci_clear8(dev, 0x78, (1 << 1));
}
--- src/southbridge/amd/sb600/sb600_pci.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-35d54e-sb600_pci.c 2010-10-05 03:02:56.505444294 +0200
@@ -32,67 +32,43 @@ static void pci_init(struct device *dev)
/* RPR 4.1 Enables the PCI-bridge subtractive decode */
/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 7;
- pci_write_config8(dev, 0x4B, byte);
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 5;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x4B, 1 << 7);
+ pci_set8(dev, 0x40, 1 << 5);
/* RPR4.2 PCI-bridge upstream dual address window */
/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
- byte = pci_read_config8(dev, 0x50);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x50, byte);
+ pci_set8(dev, 0x50, 1 << 0);
/* RPR 4.3 PCI bus 64-byte DMA read access */
/* Enhance the PCI bus DMA performance */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 4;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 4);
/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
/* The size of the writes will be set in the Cacheline Register */
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 1;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 1);
/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
pci_write_config8(dev, 0x0D, 0x40);
pci_write_config8(dev, 0x1B, 0x40);
/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 6;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 6);
/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 0);
/* RPR 4.8 Adjusts the GNT# de-assertion time */
- word = pci_read_config16(dev, 0x64);
- word |= 1 << 12;
- pci_write_config16(dev, 0x64, word);
+ pci_set16(dev, 0x64, 1 << 12);
/* RPR 4.9 Fast Back to Back transactions support */
- byte = pci_read_config8(dev, 0x48);
- byte |= 1 << 2;
- pci_write_config8(dev, 0x48, byte);
+ pci_set8(dev, 0x48, 1 << 2);
/* RPR 4.10 Enable Lock Operation */
- byte = pci_read_config8(dev, 0x48);
- byte |= 1 << 3;
- pci_write_config8(dev, 0x48, byte);
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x48, 1 << 3);
+ pci_set8(dev, 0x40, (1 << 2));
/* RPR 4.11 Enable additional optional PCI clock */
- word = pci_read_config16(dev, 0x64);
- word |= 1 << 8;
- pci_write_config16(dev, 0x64, word);
+ pci_set16(dev, 0x64, 1 << 8);
/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
byte = pci_read_config8(dev, 0x64);
@@ -100,24 +76,16 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, 0x64, byte);
/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 18);
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 18));
/* RPR 4.13 Enable One-Prefetch-Channel Mode */
- dword = pci_read_config32(dev, 0x64);
- dword |= 1 << 20;
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, 1 << 20);
/* RPR 4.15 Disable PCIB MSI Capability */
- byte = pci_read_config8(dev, 0x40);
- byte &= ~(1 << 3);
- pci_write_config8(dev, 0x40, byte);
+ pci_clear8(dev, 0x40, (1 << 3));
/* rpr4.16 Adjusting CLKRUN# */
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 15);
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 15));
}
static struct pci_operations lops_pci = {
--- src/southbridge/amd/sb600/sb600_usb.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-53c3e5-sb600_usb.c 2010-10-05 03:02:56.837444068 +0200
@@ -39,9 +39,7 @@ static void usb_init(struct device *dev)
/* Enable OHCI0-4 and EHCI Controllers */
device_t sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0x68);
- byte |= 0x3F;
- pci_write_config8(sm_dev, 0x68, byte);
+ pci_set8(sm_dev, 0x68, 0x3F);
/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
byte = pm_ioread(0x61);
@@ -62,25 +60,17 @@ static void usb_init(struct device *dev)
pm_iowrite(0x65, byte);
/* RPR 5.11 Disable OHCI MSI Capability */
- word = pci_read_config16(dev, 0x40);
- word |= (0x1F << 8);
- pci_write_config16(dev, 0x40, word);
+ pci_set16(dev, 0x40, (0x1F << 8));
/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature */
- dword = pci_read_config32(dev, 0x50);
- dword &= ~(1 << 16);
- pci_write_config32(dev, 0x50, dword);
+ pci_clear32(dev, 0x50, (1 << 16));
/* RPR 5.12 Enable prevention of OHCI accessing the invalid system memory address range */
- word = pci_read_config16(dev, 0x50);
- word |= 1 << 15;
- pci_write_config16(dev, 0x50, word);
+ pci_set16(dev, 0x50, 1 << 15);
/* RPR 5.15 Disable SMI handshake in between USB and ACPI for USB legacy support. */
/* The BIOS should always set this bit to prevent the malfunction on USB legacy keyboard/mouse support */
- word = pci_read_config16(dev, 0x50);
- word |= 1 << 12;
- pci_write_config16(dev, 0x50, word);
+ pci_set16(dev, 0x50, 1 << 12);
}
static void usb_init2(struct device *dev)
@@ -110,19 +100,13 @@ static void usb_init2(struct device *dev
write16(usb2_bar0 + 0xBC, word);
/* RPR5.10 Disable EHCI MSI support */
- byte = pci_read_config8(dev, 0x50);
- byte |= (1 << 6);
- pci_write_config8(dev, 0x50, byte);
+ pci_set8(dev, 0x50, (1 << 6));
/* RPR5.13 Disable C3 time enhancement feature */
- dword = pci_read_config32(dev, 0x50);
- dword &= ~(1 << 28);
- pci_write_config32(dev, 0x50, dword);
+ pci_clear32(dev, 0x50, (1 << 28));
/* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */
- byte = pci_read_config8(dev, 0x54);
- byte &= ~(1 << 0);
- pci_write_config8(dev, 0x54, byte);
+ pci_clear8(dev, 0x54, (1 << 0));
}
static void usb_set_resources(struct device *dev)
--- src/southbridge/amd/sb600/sb600_sata.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d0f17b-sb600_sata.c 2010-10-05 03:02:57.237444025 +0200
@@ -74,10 +74,7 @@ static void sata_init(struct device *dev
byte = pci_read_config8(sm_dev, 0xad);
byte |= (1 << 1);
/* Enable SATA and power saving */
- byte = pci_read_config8(sm_dev, 0xad);
- byte |= (1 << 0);
- byte |= (1 << 5);
- pci_write_config8(sm_dev, 0xad, byte);
+ pci_set8(sm_dev, 0xad, (1 << 0) | (1 << 5));
/* Set the interrupt Mapping to INTG# */
byte = pci_read_config8(sm_dev, 0xaf);
byte = 0x6 << 2;
@@ -103,32 +100,21 @@ static void sata_init(struct device *dev
pci_write_config32(dev, 0x2c, dword);
/* SERR-Enable */
- word = pci_read_config16(dev, 0x04);
- word |= (1 << 8);
- pci_write_config16(dev, 0x04, word);
+ pci_set16(dev, 0x04, (1 << 8));
/* Dynamic power saving */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* Set SATA Operation Mode, Set to IDE mode */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 0);
- byte |= (1 << 4);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 0) | (1 << 4));
dword = 0x01018f00;
pci_write_config32(dev, 0x8, dword);
- byte = pci_read_config8(dev, 0x40);
- byte &= ~(1 << 0);
- pci_write_config8(dev, 0x40, byte);
+ pci_clear8(dev, 0x40, (1 << 0));
/* Enable the SATA watchdog counter */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 0);
- pci_write_config8(dev, 0x44, byte);
+ pci_set8(dev, 0x44, (1 << 0));
/* Program the watchdog counter to 0x10 */
byte = 0x10;
@@ -152,18 +138,12 @@ static void sata_init(struct device *dev
pci_write_config8(dev, 0xBD, byte);
/* RPR 6.8 */
- word = pci_read_config16(dev, 0x42);
- word |= 1 << 7;
- pci_write_config16(dev, 0x42, word);
+ pci_set16(dev, 0x42, 1 << 7);
/* RPR 6.9 */
- dword = pci_read_config32(dev, 0x40);
- dword |= 1 << 25;
- pci_write_config32(dev, 0x40, dword);
+ pci_set32(dev, 0x40, 1 << 25);
/* Enable the I/O, MM, BusMaster access for SATA */
- byte = pci_read_config8(dev, 0x4);
- byte |= 7 << 0;
- pci_write_config8(dev, 0x4, byte);
+ pci_set8(dev, 0x4, 7 << 0);
/* RPR6.6 SATA drive detection. */
/* Use BAR5+0x128,BAR0 for Primary Slave */
--- src/southbridge/amd/sb600/sb600_sm.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-62ee4e-sb600_sm.c 2010-10-05 03:02:57.749443841 +0200
@@ -60,18 +60,12 @@ static void sm_init(device_t dev)
/* Don't rename APIC ID */
clear_ioapic(ioapic_base);
- dword = pci_read_config8(dev, 0x62);
- dword |= 1 << 2;
- pci_write_config8(dev, 0x62, dword);
-
- dword = pci_read_config32(dev, 0x78);
- dword |= 1 << 9;
- pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
+ pci_set8(dev, 0x62, 1 << 2);
+
+ pci_set32(dev, 0x78, 1 << 9); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
- dword = pci_read_config8(dev, 0x64);
- dword |= 1 << 10;
- pci_write_config8(dev, 0x64, dword);
+ pci_set8(dev, 0x64, 1 << 10);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
--- src/southbridge/amd/sb600/sb600_early_setup.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-389437-sb600_early_setup.c 2010-10-05 03:02:58.381444095 +0200
@@ -76,26 +76,18 @@ static void sb600_lpc_init(void)
* This bit has no meaning if debug strap is not enabled. So if the
* board keeps rebooting and the code fails to reach here, we could
* disable the debug strap first. */
- reg32 = pci_read_config32(dev, 0x4C);
- reg32 |= 1 << 31;
- pci_write_config32(dev, 0x4C, reg32);
+ pci_set32(dev, 0x4C, 1 << 31);
/* Enable lpc controller */
- reg32 = pci_read_config32(dev, 0x64);
- reg32 |= 1 << 20;
- pci_write_config32(dev, 0x64, reg32);
+ pci_set32(dev, 0x64, 1 << 20);
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
// XXX Serial port decode on LPC is hardcoded to 0x3f8
- reg8 = pci_read_config8(dev, 0x44);
- reg8 |= 1 << 6;
- pci_write_config8(dev, 0x44, reg8);
+ pci_set8(dev, 0x44, 1 << 6);
/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
- reg8 = pci_read_config8(dev, 0x47);
- reg8 |= (1 << 5) | (1 << 6);
- pci_write_config8(dev, 0x47, reg8);
+ pci_set8(dev, 0x47, (1 << 5) | (1 << 6));
/* SuperIO, LPC ROM */
reg8 = pci_read_config8(dev, 0x48);
@@ -219,40 +211,28 @@ void sb600_pci_port80(void)
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* Chip Control: Enable subtractive decoding */
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 5;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 5);
/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 7;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 7);
/* The same IO Base and IO Limit here is meaningful because we set the
* bridge to be subtractive. During early setup stage, we have to make
* sure that data can go through port 0x80.
*/
/* IO Base: 0xf000 */
- byte = pci_read_config8(dev, 0x1C);
- byte |= 0xF << 4;
- pci_write_config8(dev, 0x1C, byte);
+ pci_set8(dev, 0x1C, 0xF << 4);
/* IO Limit: 0xf000 */
- byte = pci_read_config8(dev, 0x1D);
- byte |= 0xF << 4;
- pci_write_config8(dev, 0x1D, byte);
+ pci_set8(dev, 0x1D, 0xF << 4);
/* PCI Command: Enable IO response */
- byte = pci_read_config8(dev, 0x04);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x04, byte);
+ pci_set8(dev, 0x04, 1 << 0);
/* LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
- byte = pci_read_config8(dev, 0x4A);
- byte &= ~(1 << 5); /* disable lpc port 80 */
- pci_write_config8(dev, 0x4A, byte);
+ pci_clear8(dev, 0x4A, (1 << 5));
}
void sb600_lpc_port80(void)
@@ -263,15 +243,11 @@ void sb600_lpc_port80(void)
/* Enable LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
- reg32 = pci_read_config32(dev, 0x64);
- reg32 |= 0x00100000; /* lpcEnable */
- pci_write_config32(dev, 0x64, reg32);
+ pci_set32(dev, 0x64, 0x00100000);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
- byte = pci_read_config8(dev, 0x4a);
- byte |= 1 << 5; /* enable port 80 */
- pci_write_config8(dev, 0x4a, byte);
+ pci_set8(dev, 0x4a, 1 << 5);
}
/* sbDevicesPorInitTable */
@@ -311,9 +287,7 @@ static void sb600_devices_por_init(void)
pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
- byte = pci_read_config8(dev, 0xd2);
- byte |= (1 << 0);
- pci_write_config8(dev, 0xd2, byte);
+ pci_set8(dev, 0xd2, (1 << 0));
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
@@ -341,9 +315,7 @@ static void sb600_devices_por_init(void)
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
- byte = pci_read_config8(dev, 0x62);
- byte |= 0x24;
- pci_write_config8(dev, 0x62, byte);
+ pci_set8(dev, 0x62, 0x24);
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
@@ -371,9 +343,7 @@ static void sb600_devices_por_init(void)
printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Disable prefetch */
- byte = pci_read_config8(dev, 0x63);
- byte |= 0x1;
- pci_write_config8(dev, 0x63, byte);
+ pci_set8(dev, 0x63, 0x1);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
@@ -398,9 +368,7 @@ static void sb600_devices_por_init(void)
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
/* Enable 0x480-0x4bf, 0x4700-0x470B */
- byte = pci_read_config8(dev, 0x4A);
- byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
- pci_write_config8(dev, 0x4A, byte);
+ pci_set8(dev, 0x4A, ((1 << 1) + (1 << 6)));
/* Set LPC ROM size, it has been done in sb600_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
@@ -568,18 +536,12 @@ static void sb600_pci_cfg(void)
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Eable the hidden revision ID, available after A13. */
- byte = pci_read_config8(dev, 0x70);
- byte |= (1 << 8);
- pci_write_config8(dev, 0x70, byte);
+ pci_set8(dev, 0x70, (1 << 8));
/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
- byte = pci_read_config8(dev, 0xae);
- byte |= (1 << 5);
- pci_write_config8(dev, 0xae, byte);
+ pci_set8(dev, 0xae, (1 << 5));
/* Enable watchdog decode timer */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 3);
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, (1 << 3));
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
@@ -608,9 +570,7 @@ static void sb600_pci_cfg(void)
/* LPC Device, BDF:0-20-3 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* rpr7.2 Enabling LPC DMA function. */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
@@ -625,24 +585,18 @@ static void sb600_pci_cfg(void)
/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
if (0x12 < get_sb600_revision()) {
u32 reg32;
- reg32 = pci_read_config32(dev, 0x40);
- reg32 |= (1 << 23);
- pci_write_config32(dev, 0x40, reg32);
+ pci_set32(dev, 0x40, (1 << 23));
}
/* EHCI Device, BDF:0-19-5, ehci usb controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
- byte = pci_read_config8(dev, 0x50);
- byte |= (1 << 6);
- pci_write_config8(dev, 0x50, byte);
+ pci_set8(dev, 0x50, (1 << 6));
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
- byte = pci_read_config8(dev, 0x41);
- byte |= 0x1f;
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, 0x1f);
}
--- src/southbridge/amd/sb700/sb700_early_setup.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-49d7ab-sb700_early_setup.c 2010-10-05 03:02:59.249443935 +0200
@@ -66,9 +66,7 @@ static u8 set_sb700_revision(void)
* the rivision ID, we don't have to make such a big function.
* We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
rev = 0x12;
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 0);
pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */
@@ -108,26 +106,18 @@ static void sb700_lpc_init(void)
* This bit has no meaning if debug strap is not enabled. So if the
* board keeps rebooting and the code fails to reach here, we could
* disable the debug strap first. */
- reg32 = pci_read_config32(dev, 0x4C);
- reg32 |= 1 << 31;
- pci_write_config32(dev, 0x4C, reg32);
+ pci_set32(dev, 0x4C, 1 << 31);
/* Enable lpc controller */
- reg32 = pci_read_config32(dev, 0x64);
- reg32 |= 1 << 20;
- pci_write_config32(dev, 0x64, reg32);
+ pci_set32(dev, 0x64, 1 << 20);
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
// XXX Serial port decode on LPC is hardcoded to 0x3f8
- reg8 = pci_read_config8(dev, 0x44);
- reg8 |= 1 << 6;
- pci_write_config8(dev, 0x44, reg8);
+ pci_set8(dev, 0x44, 1 << 6);
/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
- reg8 = pci_read_config8(dev, 0x47);
- reg8 |= (1 << 5) | (1 << 6);
- pci_write_config8(dev, 0x47, reg8);
+ pci_set8(dev, 0x47, (1 << 5) | (1 << 6));
/* SuperIO, LPC ROM */
reg8 = pci_read_config8(dev, 0x48);
@@ -240,40 +230,28 @@ void sb700_pci_port80(void)
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* Chip Control: Enable subtractive decoding */
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 5;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 5);
/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 7;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 7);
/* The same IO Base and IO Limit here is meaningful because we set the
* bridge to be subtractive. During early setup stage, we have to make
* sure that data can go through port 0x80.
*/
/* IO Base: 0xf000 */
- byte = pci_read_config8(dev, 0x1C);
- byte |= 0xF << 4;
- pci_write_config8(dev, 0x1C, byte);
+ pci_set8(dev, 0x1C, 0xF << 4);
/* IO Limit: 0xf000 */
- byte = pci_read_config8(dev, 0x1D);
- byte |= 0xF << 4;
- pci_write_config8(dev, 0x1D, byte);
+ pci_set8(dev, 0x1D, 0xF << 4);
/* PCI Command: Enable IO response */
- byte = pci_read_config8(dev, 0x04);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x04, byte);
+ pci_set8(dev, 0x04, 1 << 0);
/* LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
- byte = pci_read_config8(dev, 0x4A);
- byte &= ~(1 << 5); /* disable lpc port 80 */
- pci_write_config8(dev, 0x4A, byte);
+ pci_clear8(dev, 0x4A, (1 << 5));
}
void sb700_lpc_port80(void)
@@ -284,15 +262,11 @@ void sb700_lpc_port80(void)
/* Enable LPC controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
- reg32 = pci_read_config32(dev, 0x64);
- reg32 |= 0x00100000; /* lpcEnable */
- pci_write_config32(dev, 0x64, reg32);
+ pci_set32(dev, 0x64, 0x00100000);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
- byte = pci_read_config8(dev, 0x4a);
- byte |= 1 << 5; /* enable port 80 */
- pci_write_config8(dev, 0x4a, byte);
+ pci_set8(dev, 0x4a, 1 << 5);
}
/* sbDevicesPorInitTable */
@@ -332,9 +306,7 @@ static void sb700_devices_por_init(void)
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
- byte = pci_read_config8(dev, 0xd2);
- byte |= (1 << 0);
- pci_write_config8(dev, 0xd2, byte);
+ pci_set8(dev, 0xd2, (1 << 0));
/* KB2RstEnable */
pci_write_config8(dev, 0x40, 0x44);
@@ -355,9 +327,7 @@ static void sb700_devices_por_init(void)
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
- byte = pci_read_config8(dev, 0x62);
- byte |= 0x24;
- pci_write_config8(dev, 0x62, byte);
+ pci_set8(dev, 0x62, 0x24);
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */
@@ -382,9 +352,7 @@ static void sb700_devices_por_init(void)
printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
/* Disable prefetch */
- byte = pci_read_config8(dev, 0x63);
- byte |= 0x1;
- pci_write_config8(dev, 0x63, byte);
+ pci_set8(dev, 0x63, 0x1);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
@@ -409,9 +377,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
/* Enable 0x480-0x4bf, 0x4700-0x470B */
- byte = pci_read_config8(dev, 0x4A);
- byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
- pci_write_config8(dev, 0x4A, byte);
+ pci_set8(dev, 0x4A, ((1 << 1) + (1 << 6)));
/* Set LPC ROM size, it has been done in sb700_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
@@ -530,9 +496,7 @@ static void sb700_pci_cfg(void)
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable watchdog decode timer */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 3);
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, (1 << 3));
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
@@ -553,9 +517,7 @@ static void sb700_pci_cfg(void)
* comments are compatible. */
dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
/* Enabling LPC DMA function. */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
@@ -568,9 +530,7 @@ static void sb700_pci_cfg(void)
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
/* rpr7.12 SATA MSI and D3 Power State Capability. */
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 0);
if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12)
pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
else
--- src/southbridge/amd/sb700/sb700_sm.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-add399-sb700_sm.c 2010-10-05 03:03:00.041443990 +0200
@@ -63,29 +63,19 @@ static void sm_init(device_t dev)
clear_ioapic(ioapic_base);
/* 2.10 Interrupt Routing/Filtering */
- dword = pci_read_config8(dev, 0x62);
- dword |= 3;
- pci_write_config8(dev, 0x62, dword);
+ pci_set8(dev, 0x62, 3);
/* Delay back to back interrupts to the CPU. */
- dword = pci_read_config16(dev, 0x64);
- dword |= 1 << 13;
- pci_write_config16(dev, 0x64, dword);
+ pci_set16(dev, 0x64, 1 << 13);
/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
/* rpr 2.1 Enabling Legacy Interrupt */
- dword = pci_read_config8(dev, 0x62);
- dword |= 1 << 2;
- pci_write_config8(dev, 0x62, dword);
-
- dword = pci_read_config32(dev, 0x78);
- dword |= 1 << 9;
- pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
+ pci_set8(dev, 0x62, 1 << 2);
+
+ pci_set32(dev, 0x78, 1 << 9); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
- dword = pci_read_config8(dev, 0x64);
- dword |= 1 << 10;
- pci_write_config8(dev, 0x64, dword);
+ pci_set8(dev, 0x64, 1 << 10);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
@@ -94,9 +84,7 @@ static void sm_init(device_t dev)
pci_write_config8(dev, 0x69, byte);
/* IRQ0From8254 */
- byte = pci_read_config8(dev, 0x41);
- byte &= ~(1 << 7);
- pci_write_config8(dev, 0x41, byte);
+ pci_clear8(dev, 0x41, (1 << 7));
byte = pm_ioread(0x61);
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
--- src/southbridge/amd/sb700/sb700_sata.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-db020f-sb700_sata.c 2010-10-05 03:03:00.649443920 +0200
@@ -97,10 +97,7 @@ static void sata_init(struct device *dev
byte = pci_read_config8(sm_dev, 0xad);
byte |= (1 << 1);
/* Enable SATA and power saving */
- byte = pci_read_config8(sm_dev, 0xad);
- byte |= (1 << 0);
- byte |= (1 << 5);
- pci_write_config8(sm_dev, 0xad, byte);
+ pci_set8(sm_dev, 0xad, (1 << 0) | (1 << 5));
/* RPR 7.2 SATA Initialization */
/* Set the interrupt Mapping to INTG# */
@@ -127,40 +124,27 @@ static void sata_init(struct device *dev
printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
/* disable combined mode */
- byte = pci_read_config8(sm_dev, 0xAD);
- byte &= ~(1 << 3);
- pci_write_config8(sm_dev, 0xAD, byte);
+ pci_clear8(sm_dev, 0xAD, (1 << 3));
/* Program the 2C to 0x43801002 */
dword = 0x43801002;
pci_write_config32(dev, 0x2c, dword);
/* SERR-Enable */
- word = pci_read_config16(dev, 0x04);
- word |= (1 << 8);
- pci_write_config16(dev, 0x04, word);
+ pci_set16(dev, 0x04, (1 << 8));
/* Dynamic power saving */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* Set SATA Operation Mode, Set to IDE mode */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 0);
- byte |= (1 << 4);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 0) | (1 << 4));
dword = 0x01018f00;
pci_write_config32(dev, 0x8, dword);
- byte = pci_read_config8(dev, 0x40);
- byte &= ~(1 << 0);
- pci_write_config8(dev, 0x40, byte);
+ pci_clear8(dev, 0x40, (1 << 0));
/* Enable the SATA watchdog counter */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 0);
- pci_write_config8(dev, 0x44, byte);
+ pci_set8(dev, 0x44, (1 << 0));
/* Set bit 29 and 24 for A12 */
dword = pci_read_config32(dev, 0x40);
@@ -186,9 +170,7 @@ static void sata_init(struct device *dev
pci_write_config8(dev, 0x46, byte);
sb700_setup_sata_phys(dev);
/* Enable the I/O, MM, BusMaster access for SATA */
- byte = pci_read_config8(dev, 0x4);
- byte |= 7 << 0;
- pci_write_config8(dev, 0x4, byte);
+ pci_set8(dev, 0x4, 7 << 0);
/* RPR7.7 SATA drive detection. */
/* Use BAR5+0x128,BAR0 for Primary Slave */
--- src/southbridge/amd/sb700/sb700_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-460f15-sb700_ide.c 2010-10-05 03:03:01.161444037 +0200
@@ -35,27 +35,19 @@ static void ide_init(struct device *dev)
/* RPR9.1 disable MSI */
/* TODO: For A14, it should set as 1. I doubt it. */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1 << 16);
- pci_write_config32(dev, 0x70, dword);
+ pci_clear32(dev, 0x70, (1 << 16));
/* Ultra DMA mode */
/* enable UDMA */
- byte = pci_read_config8(dev, 0x54);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x54, byte);
+ pci_set8(dev, 0x54, 1 << 0);
/* Enable I/O Access&& Bus Master */
- dword = pci_read_config16(dev, 0x4);
- dword |= 1 << 2;
- pci_write_config16(dev, 0x4, dword);
+ pci_set16(dev, 0x4, 1 << 2);
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in $vendor/$mainboard/devicetree.cb */
if (conf->boot_switch_sata_ide == 1) {
- byte = pci_read_config8(dev, 0xAD);
- byte |= 1 << 4;
- pci_write_config8(dev, 0xAD, byte);
+ pci_set8(dev, 0xAD, 1 << 4);
}
#if CONFIG_PCI_ROM_RUN == 1
--- src/southbridge/amd/sb700/sb700_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-dde956-sb700_lpc.c 2010-10-05 03:03:01.385444630 +0200
@@ -37,9 +37,7 @@ static void lpc_init(device_t dev)
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword = pci_read_config32(sm_dev, 0x64);
- dword |= 1 << 20;
- pci_write_config32(sm_dev, 0x64, dword);
+ pci_set32(sm_dev, 0x64, 1 << 20);
/* Initialize isa dma */
#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
@@ -49,19 +47,13 @@ static void lpc_init(device_t dev)
#endif
/* Enable DMA transaction on the LPC bus */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 2);
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 2));
/* Disable the timeout mechanism on LPC */
- byte = pci_read_config8(dev, 0x48);
- byte &= ~(1 << 7);
- pci_write_config8(dev, 0x48, byte);
+ pci_clear8(dev, 0x48, (1 << 7));
/* Disable LPC MSI Capability */
- byte = pci_read_config8(dev, 0x78);
- byte &= ~(1 << 1);
- pci_write_config8(dev, 0x78, byte);
+ pci_clear8(dev, 0x78, (1 << 1));
}
static void sb700_lpc_read_resources(device_t dev)
--- src/southbridge/amd/sb700/sb700_pci.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ab7260-sb700_pci.c 2010-10-05 03:03:01.733444609 +0200
@@ -32,79 +32,48 @@ static void pci_init(struct device *dev)
/* RPR 5.1 Enables the PCI-bridge subtractive decode */
/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 7;
- pci_write_config8(dev, 0x4B, byte);
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 5;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x4B, 1 << 7);
+ pci_set8(dev, 0x40, 1 << 5);
/* RPR5.2 PCI-bridge upstream dual address window */
/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
- byte = pci_read_config8(dev, 0x50);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x50, byte);
+ pci_set8(dev, 0x50, 1 << 0);
/* RPR 5.3 PCI bus 64-byte DMA read access */
/* Enhance the PCI bus DMA performance */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 4;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 4);
/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
/* The size of the writes will be set in the Cacheline Register */
- byte = pci_read_config8(dev, 0x40);
- byte |= 1 << 1;
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, 1 << 1);
/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
pci_write_config8(dev, 0x0D, 0x40);
pci_write_config8(dev, 0x1B, 0x40);
/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 6;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 6);
/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1 << 0;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1 << 0);
/* RPR 5.8 Adjusts the GNT# de-assertion time */
- word = pci_read_config16(dev, 0x64);
- word |= 1 << 12;
- pci_write_config16(dev, 0x64, word);
+ pci_set16(dev, 0x64, 1 << 12);
/* RPR 5.9 Fast Back to Back transactions support */
- byte = pci_read_config8(dev, 0x48);
- byte |= 1 << 2;
- /* pci_write_config8(dev, 0x48, byte); */
-
- /* RPR 5.10 Enable Lock Operation */
- /* byte = pci_read_config8(dev, 0x48); */
- byte |= 1 << 3;
- pci_write_config8(dev, 0x48, byte);
+ pci_set8(dev, 0x48, 1 << 2 | 1 << 3);
/* RPR 5.11 Enable additional optional PCI clock */
- word = pci_read_config16(dev, 0x64);
- word |= 1 << 8;
- pci_write_config16(dev, 0x64, word);
+ pci_set16(dev, 0x64, 1 << 8);
/* RPR 5.12 Enable One-Prefetch-Channel Mode */
- dword = pci_read_config32(dev, 0x64);
- dword |= 1 << 20;
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, 1 << 20);
/* RPR 5.13 Disable PCIB MSI Capability */
- byte = pci_read_config8(dev, 0x40);
- byte &= ~(1 << 3);
- pci_write_config8(dev, 0x40, byte);
+ pci_clear8(dev, 0x40, (1 << 3));
/* rpr5.14 Adjusting CLKRUN# */
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 15);
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 15));
}
static struct pci_operations lops_pci = {
--- src/southbridge/amd/sb700/sb700_usb.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-14c970-sb700_usb.c 2010-10-05 03:03:01.985444222 +0200
@@ -38,9 +38,7 @@ static void usb_init(struct device *dev)
/* 6.1 Enable OHCI0-4 and EHCI Controllers */
device_t sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0x68);
- byte |= 0xFF;
- pci_write_config8(sm_dev, 0x68, byte);
+ pci_set8(sm_dev, 0x68, 0xFF);
/* RPR 6.2 Enables the USB PME Event,Enable USB resume support */
byte = pm_ioread(0x61);
@@ -61,9 +59,7 @@ static void usb_init(struct device *dev)
pm_iowrite(0x65, byte);
/* RPR 6.10 Disable OHCI MSI Capability. */
- word = pci_read_config16(dev, 0x40);
- word |= (0x3 << 8);
- pci_write_config16(dev, 0x40, word);
+ pci_set16(dev, 0x40, (0x3 << 8));
}
static void usb_init2(struct device *dev)
@@ -92,9 +88,7 @@ static void usb_init2(struct device *dev
write32(usb2_bar0 + 0xA4, dword);
/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
- dword = pci_read_config32(dev, 0x50);
- dword |= (1 << 28);
- pci_write_config32(dev, 0x50, dword);
+ pci_set32(dev, 0x50, (1 << 28));
/* RPR 6.12 EHCI Advance PHY Power Savings */
/* RPR says it is just for A12. CIMM sets it when it is above A11. */
@@ -107,14 +101,10 @@ static void usb_init2(struct device *dev
/* RPR6.13 Enabling Fix for EHCI Controller Dirver Yellow Sign Issue */
/* RPR says it is just for A12. CIMM sets it when it is above A11. */
- dword = pci_read_config32(dev, 0x50);
- dword |= (1 << 20);
- pci_write_config32(dev, 0x50, dword);
+ pci_set32(dev, 0x50, (1 << 20));
/* RPR6.15 EHCI Async Park Mode */
- dword = pci_read_config32(dev, 0x50);
- dword |= (1 << 23);
- pci_write_config32(dev, 0x50, dword);
+ pci_set32(dev, 0x50, (1 << 23));
/* Each step below causes the linux crashes. Leave them here
* for future debugging. */
--- src/southbridge/amd/rs690/rs690.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1b8207-rs690.c 2010-10-05 03:03:02.317444546 +0200
@@ -40,9 +40,7 @@ void static rs690_config_misc_clk(device
/* u8 byte; */
struct bus pbus; /* fake bus for dev0 fun1 */
- reg = pci_read_config32(nb_dev, 0x4c);
- reg |= 1 << 0;
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_set32(nb_dev, 0x4c, 1 << 0);
word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
word &= 0xf00;
@@ -97,9 +95,7 @@ void static rs690_config_misc_clk(device
/* TODO: */
#endif
- reg = pci_read_config32(nb_dev, 0x4c);
- reg &= ~(1 << 0);
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_clear32(nb_dev, 0x4c, (1 << 0));
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
}
--- src/southbridge/amd/rs690/rs690_ht.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-abe400-rs690_ht.c 2010-10-05 03:03:02.649447540 +0200
@@ -56,18 +56,13 @@ static void pcie_init(struct device *dev
printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* System error enable */
- dword |= (1 << 30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
/*
* 1 is APIC enable
* 18 is enable nb to accept A4 interrupt request from SB.
*/
- dword = pci_read_config32(dev, 0x4C);
- dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
- pci_write_config32(dev, 0x4C, dword);
+ pci_set32(dev, 0x4C, 1 << 1 | 1 << 18);
}
static struct pci_operations lops_pci = {
--- src/southbridge/amd/rs690/rs690_pcie.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2e7ec4-rs690_pcie.c 2010-10-05 03:03:02.861445658 +0200
@@ -114,10 +114,7 @@ static void pcie_init(struct device *dev
printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* System error enable */
- dword |= (1 << 30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
}
#endif
@@ -227,13 +224,9 @@ void rs690_gpp_sb_init(device_t nb_dev,
set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 6);
/* SLOT_IMPLEMENTED in pcieConfig space */
- reg8 = pci_read_config8(dev, 0x5b);
- reg8 |= 1 << 0;
- pci_write_config8(dev, 0x5b, reg8);
-
- reg16 = pci_read_config16(dev, 0x5a);
- reg16 |= 0x100;
- pci_write_config16(dev, 0x5a, reg16);
+ pci_set8(dev, 0x5b, 1 << 0);
+
+ pci_set16(dev, 0x5a, 0x100);
nbmisc_write_index(nb_dev, 0x34, 0);
/* check compliance rpr step 2.1*/
@@ -307,9 +300,7 @@ void rs690_gpp_sb_init(device_t nb_dev,
/* To eable L0s in the RS690 for the GPP port(s) */
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
- reg16 = pci_read_config16(dev, 0x68);
- reg16 |= 1 << 0;
- pci_write_config16(dev, 0x68, reg16);
+ pci_set16(dev, 0x68, 1 << 0);
/* step 6d: ASPM L1 for the southbridge link */
/* To enalbe L1s in the southbridage*/
@@ -366,9 +357,7 @@ void pcie_config_misc_clk(device_t nb_de
u32 reg;
struct bus pbus; /* fake bus for dev0 fun1 */
- reg = pci_read_config32(nb_dev, 0x4c);
- reg |= 1 << 0;
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_set32(nb_dev, 0x4c, 1 << 0);
if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
/* TXCLK Clock Gating */
@@ -394,8 +383,6 @@ void pcie_config_misc_clk(device_t nb_de
pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
}
- reg = pci_read_config32(nb_dev, 0x4c);
- reg &= ~(1 << 0);
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_clear32(nb_dev, 0x4c, (1 << 0));
}
#endif
--- src/southbridge/amd/rs690/rs690_gfx.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-393d56-rs690_gfx.c 2010-10-05 03:03:03.381443944 +0200
@@ -161,9 +161,7 @@ static void rs690_internal_gfx_enable(de
}
/* Set K8 MC for UMA, Family F. */
- l_dword = pci_read_config32(k8_f2, 0xa0);
- l_dword |= 0x2c;
- pci_write_config32(k8_f2, 0xa0, l_dword);
+ pci_set32(k8_f2, 0xa0, 0x2c);
l_dword = pci_read_config32(k8_f2, 0x94);
l_dword &= 0xf0ffffff;
l_dword |= 0x07000000;
@@ -555,9 +553,7 @@ void rs690_gfx_init(device_t nb_dev, dev
/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
* SLOT_IMPLEMENTED at PCIE_CAP */
- reg16 = pci_read_config16(dev, 0x5a);
- reg16 |= 0x100;
- pci_write_config16(dev, 0x5a, reg16);
+ pci_set16(dev, 0x5a, 0x100);
printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
--- src/southbridge/amd/rs780/rs780.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-261642-rs780.c 2010-10-05 03:03:04.125444235 +0200
@@ -37,9 +37,7 @@ void static rs780_config_misc_clk(device
u8 byte;
struct bus pbus; /* fake bus for dev0 fun1 */
- reg = pci_read_config32(nb_dev, 0x4c);
- reg |= 1 << 0;
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_set32(nb_dev, 0x4c, 1 << 0);
word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
word &= 0xf00;
@@ -100,9 +98,7 @@ void static rs780_config_misc_clk(device
/* TODO: */
#endif
- reg = pci_read_config32(nb_dev, 0x4c);
- reg &= ~(1 << 0);
- pci_write_config32(nb_dev, 0x4c, reg);
+ pci_clear32(nb_dev, 0x4c, (1 << 0));
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
}
@@ -126,17 +122,13 @@ static void rs780_nb_pci_table(device_t
pci_write_config8(nb_dev, 0x4c, 0x42);
- temp8 = pci_read_config8(nb_dev, 0x4e);
- temp8 |= 0x05;
- pci_write_config8(nb_dev, 0x4e, temp8);
+ pci_set8(nb_dev, 0x4e, 0x05);
temp32 = pci_read_config32(nb_dev, 0x4c);
printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
/* disable GFX debug. */
- temp8 = pci_read_config8(nb_dev, 0x8d);
- temp8 &= ~(1<<1);
- pci_write_config8(nb_dev, 0x8d, temp8);
+ pci_clear8(nb_dev, 0x8d, (1 << 1));
/* set temporary NB TOM to 0x40000000. */
rs780_set_tom(nb_dev);
--- src/southbridge/amd/rs780/rs780_early_setup.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d508d3-rs780_early_setup.c 2010-10-05 03:03:04.681444087 +0200
@@ -391,19 +391,13 @@ static void fam10_optimization(void)
pci_write_config32(cpu_f0, 0x94, 0x00000000);
/* Table 8-15 */
- val = pci_read_config32(cpu_f0, 0x68);
- val |= 1 << 24;
- pci_write_config32(cpu_f0, 0x68, val);
+ pci_set32(cpu_f0, 0x68, 1 << 24);
/* Table 8-16 */
- val = pci_read_config32(cpu_f0, 0x84);
- val &= ~(1 << 12);
- pci_write_config32(cpu_f0, 0x84, val);
+ pci_clear32(cpu_f0, 0x84, (1 << 12));
/* Table 8-17 */
- val = pci_read_config32(cpu_f2, 0x90);
- val &= ~(1 << 10);
- pci_write_config32(cpu_f2, 0x90, val);
+ pci_clear32(cpu_f2, 0x90, (1 << 10));
/* Table 8-18 */
pci_write_config32(cpu_f3, 0x6C, 0x60018051);
--- src/southbridge/amd/rs780/rs780_gfx.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b26cc0-rs780_gfx.c 2010-10-05 03:03:05.701443884 +0200
@@ -319,9 +319,7 @@ static void internal_gfx_pci_dev_init(st
printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
deviceid, vendorid);
- command = pci_read_config16(dev, 0x04);
- command |= 0x7;
- pci_write_config16(dev, 0x04, command);
+ pci_set16(dev, 0x04, 0x7);
/* Clear vgainfo. */
bpointer = (unsigned char *) &vgainfo;
@@ -492,10 +490,7 @@ static void internal_gfx_pci_dev_init(st
/* GFX_InitLate. */
{
u8 temp8;
- temp8 = pci_read_config8(dev, 0x4);
- //temp8 &= ~1; /* CIM clears this bit. Strangely, I can'd. */
- temp8 |= 1<<1|1<<2;
- pci_write_config8(dev, 0x4, temp8);
+ pci_set8(dev, 0x4, 1 << 1 | 1 << 2);
}
#ifdef DONT_TRUST_RESOURCE_ALLOCATION
--- src/southbridge/amd/rs780/rs780_ht.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-bbe852-rs780_ht.c 2010-10-05 03:03:07.833458349 +0200
@@ -56,18 +56,13 @@ static void pcie_init(struct device *dev
printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* System error enable */
- dword |= (1 << 30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
/*
* 1 is APIC enable
* 18 is enable nb to accept A4 interrupt request from SB.
*/
- dword = pci_read_config32(dev, 0x4C);
- dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
- pci_write_config32(dev, 0x4C, dword);
+ pci_set32(dev, 0x4C, 1 << 1 | 1 << 18);
}
static struct pci_operations lops_pci = {
--- src/southbridge/amd/cs5530/cs5530_enable_rom.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-5729bc-cs5530_enable_rom.c 2010-10-05 03:03:08.177448361 +0200
@@ -41,7 +41,5 @@ static void cs5530_enable_rom(void)
pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
/* Set positive decode on ROM. */
- reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
- reg8 |= BIOS_ROM_POSITIVE_DECODE;
- pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+ pci_set8(dev, DECODE_CONTROL_REG2, BIOS_ROM_POSITIVE_DECODE);
}
--- src/southbridge/amd/cs5536/cs5536_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-08a7b3-cs5536_ide.c 2010-10-05 03:03:08.413453051 +0200
@@ -41,9 +41,7 @@ static void ide_init(struct device *dev)
// Enable the channel and Post Write Buffer
// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
- ide_cfg = pci_read_config32(dev, IDE_CFG);
- ide_cfg |= CHANEN | PWB;
- pci_write_config32(dev, IDE_CFG, ide_cfg);
+ pci_set32(dev, IDE_CFG, CHANEN | PWB);
}
static struct device_operations ide_ops = {
--- src/southbridge/amd/amd8111/amd8111_early_ctrl.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-882ef8-amd8111_early_ctrl.c 2010-10-05 03:03:08.681451429 +0200
@@ -24,9 +24,7 @@ static void enable_cf9_x(unsigned sbbusn
dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
/* enable cf9 */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1<<6) | (1<<5);
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, (1 << 6) | (1 << 5));
}
static void enable_cf9(void)
--- src/southbridge/amd/amd8111/amd8111_acpi.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-71d21a-amd8111_acpi.c 2010-10-05 03:03:08.973450602 +0200
@@ -171,9 +171,7 @@ static void acpi_enable_resources(device
pci_dev_enable_resources(dev);
/* Enable the ACPI/SMBUS Bar */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 7);
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, (1 << 7));
/* Set the class code */
pci_write_config32(dev, 0x60, 0x06800000);
--- src/southbridge/amd/amd8111/amd8111_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2f7778-amd8111_lpc.c 2010-10-05 03:03:09.433450711 +0200
@@ -32,9 +32,7 @@ static void lpc_init(struct device *dev)
int nmi_option;
/* IO APIC initialization */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1;
- pci_write_config8(dev, 0x4B, byte);
+ pci_set8(dev, 0x4B, 1);
/* Don't rename IO APIC */
setup_ioapic(IO_APIC_ADDR, 0);
@@ -43,26 +41,17 @@ static void lpc_init(struct device *dev)
pci_write_config8(dev, 0x46, byte | (1<<0));
/* Enable 5Mib Rom window */
- byte = pci_read_config8(dev, 0x43);
- byte |= 0xc0;
- pci_write_config8(dev, 0x43, byte);
+ pci_set8(dev, 0x43, 0xc0);
/* Enable Port 92 fast reset */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 5);
- pci_write_config8(dev, 0x41, byte);
+ pci_set8(dev, 0x41, (1 << 5));
/* Enable Error reporting */
/* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
+ pci_set8(dev, 0x47, (1 << 1));
/* Set up NMI on errors */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 1); /* clear PW2LPC error */
- byte |= (1 << 6); /* clear LPCERR */
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 1) | (1 << 6));
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
--- src/southbridge/amd/amd8111/amd8111_pci.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-722e40-amd8111_pci.c 2010-10-05 03:03:09.772444020 +0200
@@ -12,10 +12,7 @@ static void pci_init(struct device *dev)
uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (7<<28); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (7 << 28));
/* System,Parity,timer,and abort error enable */
dword = pci_read_config32(dev, 0x3c);
--- src/southbridge/amd/amd8131/amd8131_bridge.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-e3782e-amd8131_bridge.c 2010-10-05 03:03:10.056443928 +0200
@@ -239,9 +239,7 @@ static unsigned int amd8131_scan_bus(str
bus->dev->enabled = 0;
/* Disable the PCI-X clocks */
- pcix_misc = pci_read_config32(bus->dev, 0x40);
- pcix_misc &= ~(0x1f << 16);
- pci_write_config32(bus->dev, 0x40, pcix_misc);
+ pci_clear32(bus->dev, 0x40, (0x1f << 16));
return max;
}
@@ -281,9 +279,7 @@ static void amd8131_pcix_init(device_t d
int nmi_option;
/* Enable memory write and invalidate ??? */
- byte = pci_read_config8(dev, 0x04);
- byte |= 0x10;
- pci_write_config8(dev, 0x04, byte);
+ pci_set8(dev, 0x04, 0x10);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
@@ -300,9 +296,7 @@ static void amd8131_pcix_init(device_t d
/* Set discard unrequested prefetch data */
/* Errata #51 */
- word = pci_read_config16(dev, 0x4c);
- word |= 1;
- pci_write_config16(dev, 0x4c, word);
+ pci_set16(dev, 0x4c, 1);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
@@ -312,33 +306,23 @@ static void amd8131_pcix_init(device_t d
/* Set up error reporting, enable all */
/* system error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8));
/* system and error parity enable */
- dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ pci_set32(dev, 0x3c, (3 << 16));
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
- dword = pci_read_config32(dev, 0x44);
- dword |= (1<<0);
- pci_write_config32(dev, 0x44, dword);
+ pci_set32(dev, 0x44, (1 << 0));
}
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
- dword = pci_read_config32(dev, 0xc4);
- dword |= (1<<1);
- pci_write_config32(dev, 0xc4, dword);
- dword = pci_read_config32(dev, 0xc8);
- dword |= (1<<1);
- pci_write_config32(dev, 0xc8, dword);
+ pci_set32(dev, 0xc4, (1 << 1));
+ pci_set32(dev, 0xc8, (1 << 1));
}
return;
}
--- src/southbridge/amd/amd8132/amd8132_bridge.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1dc0e4-amd8132_bridge.c 2010-10-05 03:03:10.700444328 +0200
@@ -240,14 +240,10 @@ static void amd8132_pcix_init(device_t d
/* Set up error reporting, enable all */
/* system error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8));
/* system and error parity enable */
- dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ pci_set32(dev, 0x3c, (3 << 16));
dword = pci_read_config32(dev, 0x40);
// dword &= ~(1<<31); /* WriteChainEnable */
@@ -267,21 +263,14 @@ static void amd8132_pcix_init(device_t d
dword |= (0x61<<24); //LPMARBCOUNT
pci_write_config32(dev, 0x48, dword);
- dword = pci_read_config32(dev, 0x4c);
- dword |= (1<<6); //intial prefetch for memory read line request
- dword |= (1<<9); //continuous prefetch Enable for memory read line request
- pci_write_config32(dev, 0x4c, dword);
+ pci_set32(dev, 0x4c, (1 << 6) | (1 << 9));
/* Disable Single-Bit-Error Correction [30] = 0 */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1<<30);
- pci_write_config32(dev, 0x70, dword);
+ pci_clear32(dev, 0x70, (1 << 30));
//link
- dword = pci_read_config32(dev, 0xd4);
- dword |= (0x5c<<16);
- pci_write_config32(dev, 0xd4, dword);
+ pci_set32(dev, 0xd4, (0x5c << 16));
/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
dword = pci_read_config32(dev, 0xdc);
@@ -304,9 +293,7 @@ static void amd8132_pcix_init(device_t d
if (chip_rev == 0x11) {
/* [18] Clock Gate Enable = 1 */
- dword = pci_read_config32(dev, 0xf0);
- dword |= 0x00040008;
- pci_write_config32(dev, 0xf0, dword);
+ pci_set32(dev, 0xf0, 0x00040008);
}
}
@@ -401,12 +388,8 @@ static void amd8132_ioapic_init(device_t
if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
//for b1 b2
/* Errata #73 */
- dword = pci_read_config32(dev, 0x80);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x80, dword);
- dword = pci_read_config32(dev, 0x88);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x88, dword);
+ pci_set32(dev, 0x80, (0x1f << 5));
+ pci_set32(dev, 0x88, (0x1f << 5));
/* Errata #74 */
dword = pci_read_config32(dev, 0x7c);
--- src/southbridge/amd/amd8151/amd8151_agp3.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b14863-amd8151_agp3.c 2010-10-05 03:03:11.360443934 +0200
@@ -40,14 +40,10 @@ static void agp3dev_enable(device_t dev)
uint32_t value;
/* AGP enable */
- value = pci_read_config32(dev, 0xa8);
- value |= (3<<8)|2; //AGP 8x
- pci_write_config32(dev, 0xa8, value);
+ pci_set32(dev, 0xa8, (3 << 8) | 2);
/* enable BM and MEM */
- value = pci_read_config32(dev, 0x4);
- value |= 6;
- pci_write_config32(dev, 0x4, value);
+ pci_set32(dev, 0x4, 6);
#if 0
/* FIXME: should we add agp aperture base and size here ?
* or it is done by AGP drivers */
--- src/southbridge/sis/sis966/sis966_early_setup_car.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-45d5bb-sis966_early_setup_car.c 2010-10-05 03:03:11.640444100 +0200
@@ -29,9 +29,7 @@ void sis966_early_pcie_setup(unsigned bu
int i;
device_t dev;
dev = PCI_DEV(busnx, devnx+1, 1);
- dword = pci_read_config32(dev, 0xe4);
- dword |= 0x3f0; // disable it at first
- pci_write_config32(dev, 0xe4, dword);
+ pci_set32(dev, 0xe4, 0x3f0);
for(i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -53,9 +51,7 @@ void sis966_early_pcie_setup(unsigned bu
// wait 100us
udelay(100);
- dword = pci_read_config32(dev, 0xe4);
- dword &= ~(0x3f0); // enable
- pci_write_config32(dev, 0xe4, dword);
+ pci_clear32(dev, 0xe4, (0x3f0));
// need to wait 100ms
mdelay(100);
--- src/southbridge/sis/sis966/sis966.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-18667b-sis966.c 2010-10-05 03:03:11.912444022 +0200
@@ -173,9 +173,7 @@ void sis966_enable(device_t dev)
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
- final_reg = pci_read_config32(sm_dev, 0xe8);
- final_reg &= ~0x0057cf00;
- pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+ pci_clear32(sm_dev, 0xe8, 0x0057cf00); //enable all at first
}
if (!dev->enabled) {
--- src/southbridge/sis/sis966/sis966_ide.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-617418-sis966_ide.c 2010-10-05 03:03:12.316443956 +0200
@@ -140,9 +140,7 @@ print_debug("IDE_INIT:---------->\n");
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
- dword = pci_read_config32(dev, 0xf8);
- dword |= 12;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 12);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
--- src/southbridge/sis/sis966/sis966_lpc.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-a0d0a1-sis966_lpc.c 2010-10-05 03:03:12.736443792 +0200
@@ -63,9 +63,7 @@ static void lpc_common_init(device_t dev
uint32_t ioapic_base;
/* IO APIC initialization */
- byte = pci_read_config8(dev, 0x74);
- byte |= (1<<0); // enable APIC
- pci_write_config8(dev, 0x74, byte);
+ pci_set8(dev, 0x74, (1 << 0));
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
@@ -130,9 +128,7 @@ static void lpc_init(device_t dev)
/* Enable Error reporting */
/* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
+ pci_set8(dev, 0x47, (1 << 1));
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
--- src/southbridge/sis/sis966/sis966_nic.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-965067-sis966_nic.c 2010-10-05 03:03:13.352452844 +0200
@@ -119,9 +119,7 @@ static void set_apc(struct device *dev)
outl(inl(0xcfc)&0xffffffbf,0xcfc);
// CFG reg0x73 bit=1, tell driver MAC Address load to APC
- bTmp = pci_read_config8(dev, 0x73);
- bTmp|=0x1;
- pci_write_config8(dev, 0x73, bTmp);
+ pci_set8(dev, 0x73, 0x1);
}
//-----------------------------------------------------------------------------
--- src/southbridge/sis/sis966/sis966_pcie.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-5f2ece-sis966_pcie.c 2010-10-05 03:03:14.052452108 +0200
@@ -37,10 +37,7 @@ static void pcie_init(struct device *dev
uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
}
--- src/southbridge/via/k8t890/k8t890_early_car.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-dfd8cb-k8t890_early_car.c 2010-10-05 03:03:14.316454049 +0200
@@ -54,9 +54,7 @@ u8 k8t890_early_setup_ht(void)
*/
pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
- reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
- reg |= 0x1;
- pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
+ pci_set8(PCI_DEV(0, 0x0, 2), 0xa1, 0x1);
/* check if connected non coherent, initcomplete (find the SB on K8 side) */
ldtnr = 0;
--- src/southbridge/via/k8t890/k8t890_ctrl.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-2300c6-k8t890_ctrl.c 2010-10-05 03:03:14.660444167 +0200
@@ -120,17 +120,13 @@ static void vt8237r_vlink_init(struct de
pci_write_config8(dev, 0xb6, 0x88);
pci_write_config8(dev, 0xb7, 0x61);
- reg = pci_read_config8(dev, 0xb4);
- reg |= 0x11;
- pci_write_config8(dev, 0xb4, reg);
+ pci_set8(dev, 0xb4, 0x11);
pci_write_config8(dev, 0xb9, 0x98);
pci_write_config8(dev, 0xba, 0x77);
pci_write_config8(dev, 0xbb, 0x11);
- reg = pci_read_config8(dev, 0xb8);
- reg |= 0x1;
- pci_write_config8(dev, 0xb8, reg);
+ pci_set8(dev, 0xb8, 0x1);
pci_write_config8(dev, 0xb0, 0x06);
pci_write_config8(dev, 0xb1, 0x01);
--- src/southbridge/via/k8t890/k8t890_host.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-d31f46-k8t890_host.c 2010-10-05 03:03:14.940445492 +0200
@@ -37,19 +37,13 @@ static void host_init(struct device *dev
u8 reg;
/* AGP Capability Header Control */
- reg = pci_read_config8(dev, 0x4d);
- reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
- pci_write_config8(dev, 0x4d, reg);
+ pci_set8(dev, 0x4d, 0x20);
/* GD Output Stagger Delay */
- reg = pci_read_config8(dev, 0x42);
- reg |= 0x10; /* AD[31:16] with 1ns */
- pci_write_config8(dev, 0x42, reg);
+ pci_set8(dev, 0x42, 0x10);
/* AGP Control */
- reg = pci_read_config8(dev, 0xbc);
- reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
- pci_write_config8(dev, 0xbc, reg);
+ pci_set8(dev, 0xbc, 0x20);
}
--- src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-6032a0-k8t890_traf_ctrl.c 2010-10-05 03:03:15.164444389 +0200
@@ -38,10 +38,7 @@ static void mmconfig_set_resources(devic
resource->flags |= IORESOURCE_STORED;
pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
(resource->base >> 28));
- reg = pci_read_config8(dev, 0x60);
- reg |= 0x3;
- /* Enable MMCONFIG decoding. */
- pci_write_config8(dev, 0x60, reg);
+ pci_set8(dev, 0x60, 0x3);
}
pci_dev_set_resources(dev);
}
--- src/southbridge/via/k8t890/k8t890_bridge.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-1561fe-k8t890_bridge.c 2010-10-05 03:03:15.620463908 +0200
@@ -47,9 +47,7 @@ static void bridge_enable(struct device
dump_south(dev);
/* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
- tmp = pci_read_config8(dev, PCI_COMMAND);
- tmp &= ~0x3;
- pci_write_config8(dev, PCI_COMMAND, tmp);
+ pci_clear8(dev, PCI_COMMAND, 0x3);
}
--- src/southbridge/via/vt8231/vt8231_early_smbus.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ad6c08-vt8231_early_smbus.c 2010-10-05 03:03:15.900448608 +0200
@@ -36,16 +36,12 @@ static void enable_smbus(void)
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
// Enable SMBus
- c = pci_read_config8(dev, 0xd2);
- c |= 5;
- pci_write_config8(dev, 0xd2, c);
+ pci_set8(dev, 0xd2, 5);
/* make it work for I/O ...
*/
dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
- c = pci_read_config8(dev, 4);
- c |= 1;
- pci_write_config8(dev, 4, c);
+ pci_set8(dev, 4, 1);
print_debug_hex8(c);
print_debug(" is the comm register\n");
--- src/southbridge/via/vt8231/vt8231_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-64e52f-vt8231_ide.c 2010-10-05 03:03:16.292455708 +0200
@@ -37,9 +37,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
- enables = pci_read_config8(dev, 0x41);
- enables |= 0xf0;
- pci_write_config8(dev, 0x41, enables);
+ pci_set8(dev, 0x41, 0xf0);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
--- src/southbridge/via/vt8231/vt8231_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9ae2cf-vt8231_lpc.c 2010-10-05 03:03:16.584447231 +0200
@@ -58,9 +58,7 @@ static void vt8231_init(struct device *d
printk(BIOS_DEBUG, "vt8231 init\n");
// enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
+ pci_set8(dev, 0x6C, 0x80);
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
@@ -72,28 +70,20 @@ static void vt8231_init(struct device *d
pci_write_config8(dev, 0x40, enables);
// Set 0x42 to 0xf0 to match Award bios
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
+ pci_set8(dev, 0x42, 0xf0);
// Set bit 3 of 0x4a, to match award (dummy pci request)
- enables = pci_read_config8(dev, 0x4a);
- enables |= 0x08;
- pci_write_config8(dev, 0x4a, enables);
+ pci_set8(dev, 0x4a, 0x08);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
// enable the ethernet/RTC
if (dev) {
- enables = pci_read_config8(dev, 0x51);
- enables |= 0x18;
- pci_write_config8(dev, 0x51, enables);
+ pci_set8(dev, 0x51, 0x18);
}
// enable IDE, since Linux won't do it.
--- src/southbridge/via/vt8231/vt8231_nic.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-f4bf29-vt8231_nic.c 2010-10-05 03:03:16.888444556 +0200
@@ -15,9 +15,7 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
- byte = pci_read_config8(dev, PCI_COMMAND);
- byte &= ~PCI_COMMAND_WAIT;
- pci_write_config8(dev, PCI_COMMAND, byte);
+ pci_clear8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
}
static struct device_operations nic_ops = {
--- src/southbridge/via/vt8231/vt8231_early_serial.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ddc598-vt8231_early_serial.c 2010-10-05 03:03:17.092446248 +0200
@@ -44,9 +44,7 @@ static void enable_vt8231_serial(void)
/* first, you have to enable the superio and superio config.
put a 6 reg 80
*/
- c = pci_read_config8(dev, 0x50);
- c |= 6;
- pci_write_config8(dev, 0x50, c);
+ pci_set8(dev, 0x50, 6);
outb(2, 0x80);
// now go ahead and set up com1.
// set address
--- src/southbridge/via/vt8231/vt8231.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-7b055d-vt8231.c 2010-10-05 03:03:17.288449909 +0200
@@ -17,9 +17,7 @@ static void keyboard_on(void)
unsigned char regval;
if (lpc_dev) {
- regval = pci_read_config8(lpc_dev, 0x51);
- regval |= 0x0f;
- pci_write_config8(lpc_dev, 0x51, regval);
+ pci_set8(lpc_dev, 0x51, 0x0f);
}
pc_keyboard_init(0);
}
--- src/southbridge/via/vt8235/vt8235_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-8a9892-vt8235_ide.c 2010-10-05 03:03:17.476444953 +0200
@@ -37,9 +37,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
- enables = pci_read_config8(dev, 0x41);
- enables |= 0xf0;
- pci_write_config8(dev, 0x41, enables);
+ pci_set8(dev, 0x41, 0xf0);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
--- src/southbridge/via/vt8235/vt8235_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9b1de3-vt8235_lpc.c 2010-10-05 03:03:17.712444236 +0200
@@ -156,9 +156,7 @@ static void vt8235_init(struct device *d
printk(BIOS_DEBUG, "vt8235 init\n");
// enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
+ pci_set8(dev, 0x6C, 0x80);
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
@@ -166,32 +164,22 @@ static void vt8235_init(struct device *d
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x45;
- pci_write_config8(dev, 0x40, enables);
+ pci_set8(dev, 0x40, 0x45);
// Set 0x42 to 0xf0 to match Award bios
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
+ pci_set8(dev, 0x42, 0xf0);
/* Set 0x58 to 0x03 to match Award */
pci_write_config8(dev, 0x58, 0x03);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
// Set bit 3 of 0x4a, to match award (dummy pci request)
- enables = pci_read_config8(dev, 0x4a);
- enables |= 0x08;
- pci_write_config8(dev, 0x4a, enables);
+ pci_set8(dev, 0x4a, 0x08);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
--- src/southbridge/via/vt8235/vt8235_nic.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d67e45-vt8235_nic.c 2010-10-05 03:03:18.172462278 +0200
@@ -15,9 +15,7 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
/* We don't need stepping - though the device supports it */
- byte = pci_read_config8(dev, PCI_COMMAND);
- byte &= ~PCI_COMMAND_WAIT;
- pci_write_config8(dev, PCI_COMMAND, byte);
+ pci_clear8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
}
static struct device_operations nic_ops = {
--- src/southbridge/via/vt8235/vt8235.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c1383a-vt8235.c 2010-10-05 03:03:18.412453259 +0200
@@ -68,9 +68,7 @@ static void vt8235_enable(struct device
setup_i8259();
/* enable RTC and ethernet */
- regval = pci_read_config8(dev, 0x51);
- regval |= 0x18;
- pci_write_config8(dev, 0x51, regval);
+ pci_set8(dev, 0x51, 0x18);
/* turn on keyboard */
keyboard_on(dev);
@@ -78,9 +76,7 @@ static void vt8235_enable(struct device
/* enable USB 1.1 & USB 2.0 - redundant really since we've
* already been there - see note above
*/
- regval = pci_read_config8(dev, 0x50);
- regval &= ~(0x36);
- pci_write_config8(dev, 0x50, regval);
+ pci_clear8(dev, 0x50, (0x36));
}
struct chip_operations southbridge_via_vt8235_ops = {
--- src/southbridge/via/vt8237r/vt8237r_sata.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-4cb8b6-vt8237r_sata.c 2010-10-05 03:03:18.656447930 +0200
@@ -70,9 +70,7 @@ static void sata_ii_init(struct device *
pci_write_config8(dev, 0x65, reg);
/* Set all manual termination 50ohm bits [2:0] and enable [4]. */
- reg = pci_read_config8(dev, 0x6a);
- reg |= 0xf;
- pci_write_config8(dev, 0x6a, reg);
+ pci_set8(dev, 0x6a, 0xf);
/*
* Analog PHY - gen2
--- src/southbridge/via/vt8237r/vt8237_ctrl.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-0dac21-vt8237_ctrl.c 2010-10-05 03:03:18.916444572 +0200
@@ -120,9 +120,7 @@ static void vt8237s_vlink_init(struct de
*/
/* disable auto disconnect */
- reg = pci_read_config8(devfun7, 0x42);
- reg &= ~0x4;
- pci_write_config8(devfun7, 0x42, reg);
+ pci_clear8(devfun7, 0x42, 0x4);
/* NB part setup */
pci_write_config8(devfun7, 0xb5, 0x66);
@@ -148,17 +146,13 @@ static void vt8237s_vlink_init(struct de
reg &= ~0x4;
pci_write_config8(dev, 0xbd, reg);
- reg = pci_read_config8(dev, 0xbc);
- reg &= ~0x7;
- pci_write_config8(dev, 0xbc, reg);
+ pci_clear8(dev, 0xbc, 0x7);
/* Program V-link 8X 8bit full duplex, parity enabled. */
pci_write_config8(dev, 0x48, 0x23 | 0x80);
/* enable auto disconnect, for STPGNT and HALT */
- reg = pci_read_config8(devfun7, 0x42);
- reg |= 0x7;
- pci_write_config8(devfun7, 0x42, reg);
+ pci_set8(devfun7, 0x42, 0x7);
}
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-1ff234-vt8237r_early_smbus.c 2010-10-05 03:03:19.216444421 +0200
@@ -413,9 +413,7 @@ int vt8237_early_network_init(struct vt8
return 0;
}
- tmp = pci_read_config32(dev, 0x5c);
- tmp |= 0x08000000; /* Enable ERDBG. */
- pci_write_config32(dev, 0x5c, tmp);
+ pci_set32(dev, 0x5c, 0x08000000);
status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3);
--- src/southbridge/via/vt8237r/vt8237r_ide.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-8c360c-vt8237r_ide.c 2010-10-05 03:03:19.708445034 +0200
@@ -53,16 +53,12 @@ static void ide_init(struct device *dev)
enables &= 0xFA;
pci_write_config8(dev, 0x09, enables);
- enables = pci_read_config8(dev, IDE_CONF_II);
- enables &= ~0xc0;
- pci_write_config8(dev, IDE_CONF_II, enables);
+ pci_clear8(dev, IDE_CONF_II, 0xc0);
enables = pci_read_config8(dev, IDE_CONF_II);
printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
/* Enable prefetch buffers. */
- enables = pci_read_config8(dev, IDE_CONF_I);
- enables |= 0xf0;
- pci_write_config8(dev, IDE_CONF_I, enables);
+ pci_set8(dev, IDE_CONF_I, 0xf0);
/* Flush FIFOs at half. */
enables = pci_read_config8(dev, IDE_CONF_FIFO);
--- src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-90af6c-vt8237r_lpc.c 2010-10-05 03:03:19.984443978 +0200
@@ -257,22 +257,16 @@ static void vt8237r_init(struct device *
* Setup to match EPIA default
* PCS0# on Pin U1
*/
- enables = pci_read_config8(dev, 0xe5);
- enables |= 0x23;
- pci_write_config8(dev, 0xe5, enables);
+ pci_set8(dev, 0xe5, 0x23);
/*
* Enable Flash Write Access.
* Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
*/
- enables = pci_read_config8(dev, 0xe4);
- enables |= 0x2B;
- pci_write_config8(dev, 0xe4, enables);
+ pci_set8(dev, 0xe4, 0x2B);
/* Enables Extra RTC Ports */
- enables = pci_read_config8(dev, 0x4E);
- enables |= 0x80;
- pci_write_config8(dev, 0x4E, enables);
+ pci_set8(dev, 0x4E, 0x80);
#else
printk(BIOS_SPEW, "Entering vt8237r_init.\n");
@@ -287,9 +281,7 @@ static void vt8237r_init(struct device *
#endif
/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
+ pci_set8(dev, 0x4f, 0x08);
#if CONFIG_EPIA_VT8237R_INIT
/*
@@ -360,16 +352,12 @@ static void vt8237_common_init(struct de
u8 enables, byte;
/* Enable addr/data stepping. */
- byte = pci_read_config8(dev, PCI_COMMAND);
- byte |= PCI_COMMAND_WAIT;
- pci_write_config8(dev, PCI_COMMAND, byte);
+ pci_set8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
/* EPIA-N(L) Uses CN400 for BIOS Access */
#if !CONFIG_EPIA_VT8237R_INIT
/* Enable the internal I/O decode. */
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
+ pci_set8(dev, 0x6C, 0x80);
/*
* ROM decode
@@ -392,14 +380,10 @@ static void vt8237_common_init(struct de
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
* that PCI interrupts can be properly marked as level triggered.
*/
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x44;
- pci_write_config8(dev, 0x40, enables);
+ pci_set8(dev, 0x40, 0x44);
/* Line buffer control */
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf8;
- pci_write_config8(dev, 0x42, enables);
+ pci_set8(dev, 0x42, 0xf8);
/* Delay transaction control */
pci_write_config8(dev, 0x43, 0xb);
--- src/southbridge/via/vt8237r/vt8237r_usb.c 2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-654cc6-vt8237r_usb.c 2010-10-05 03:03:20.516444329 +0200
@@ -49,9 +49,7 @@ static void usb_i_init(struct device *de
pci_write_config8(dev, 0x0d, 0x20);
/* Enable Sub Device ID Back Door and set Generic */
- reg8 = pci_read_config8(dev, 0x42);
- reg8 |= 0x10;
- pci_write_config8(dev, 0x42, reg8);
+ pci_set8(dev, 0x42, 0x10);
pci_write_config16(dev, 0x2e, 0xAA07);
reg8 &= ~0x10;
pci_write_config8(dev, 0x42, reg8);
@@ -100,9 +98,7 @@ static void usb_ii_init(struct device *d
printk(BIOS_DEBUG, "Entering %s\n", __func__);
/* Set memory Write and Invalidate */
- reg8 = pci_read_config8(dev, 0x04);
- reg8 |= 0x10;
- pci_write_config8(dev, 0x04, reg8);
+ pci_set8(dev, 0x04, 0x10);
/* Set Cache line Size and Latency Timer */
pci_write_config8(dev, 0x0c, 0x08);
--- src/southbridge/intel/pxhd/pxhd_bridge.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-c5f225-pxhd_bridge.c 2010-10-05 03:03:20.808444207 +0200
@@ -163,9 +163,7 @@ static void ioapic_init(device_t dev)
{
uint32_t value, ioapic_base;
/* Enable bus mastering so IOAPICs work */
- value = pci_read_config16(dev, PCI_COMMAND);
- value |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, value);
+ pci_set16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
--- src/southbridge/intel/i3100/i3100_lpc.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-b469a9-i3100_lpc.c 2010-10-05 03:03:21.144444042 +0200
@@ -393,14 +393,10 @@ static void i3100_lpc_enable_resources(d
pci_dev_enable_resources(dev);
/* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 7);
- pci_write_config8(dev, 0x44, acpi_cntl);
+ pci_set8(dev, 0x44, (1 << 7));
/* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x4c);
- gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x4c, gpio_cntl);
+ pci_set8(dev, 0x4c, (1 << 4));
/* Enable the RCBA */
pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
--- src/southbridge/intel/i82371eb/i82371eb_early_pm.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-80af32-i82371eb_early_pm.c 2010-10-05 03:03:21.668447323 +0200
@@ -41,13 +41,9 @@ static void enable_pm(void)
pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
/* Enable access to the PM I/O space. */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_IO;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_set16(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* PM I/O Space Enable (PMIOSE). */
- reg8 = pci_read_config8(dev, PMREGMISC);
- reg8 |= PMIOSE;
- pci_write_config8(dev, PMREGMISC, reg8);
+ pci_set8(dev, PMREGMISC, PMIOSE);
}
--- src/southbridge/intel/i82371eb/i82371eb_early_smbus.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-e9dc9a-i82371eb_early_smbus.c 2010-10-05 03:03:21.880444089 +0200
@@ -44,14 +44,10 @@ static void enable_smbus(void)
pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
/* Enable the SMBus controller host interface. */
- reg8 = pci_read_config8(dev, SMBHSTCFG);
- reg8 |= SMB_HST_EN;
- pci_write_config8(dev, SMBHSTCFG, reg8);
+ pci_set8(dev, SMBHSTCFG, SMB_HST_EN);
/* Enable access to the SMBus I/O space. */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_IO;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_set16(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* Clear any lingering errors, so the transaction will run. */
outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
--- src/southbridge/intel/i82801ax/i82801ax_watchdog.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-8fad66-i82801ax_watchdog.c 2010-10-05 03:03:22.132444328 +0200
@@ -35,9 +35,7 @@ void watchdog_off(void)
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
/* Enable I/O space. */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Get TCO base. */
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801ax/i82801ax_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-c63a14-i82801ax_pci.c 2010-10-05 03:03:22.384443905 +0200
@@ -29,13 +29,9 @@ static void pci_init(struct device *dev)
uint16_t reg16;
/* Clear system errors */
- reg16 = pci_read_config16(dev, 0x06);
- reg16 |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, reg16);
-
- reg16 = pci_read_config16(dev, 0x1e);
- reg16 |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, reg16);
+ pci_set16(dev, 0x06, 0xf900);
+
+ pci_set16(dev, 0x1e, 0xf800);
}
static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801bx/i82801bx_watchdog.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3c7627-i82801bx_watchdog.c 2010-10-05 03:03:22.632444196 +0200
@@ -35,9 +35,7 @@ void watchdog_off(void)
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
/* Enable I/O space. */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Get TCO base. */
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801bx/i82801bx_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-e6dfb6-i82801bx_pci.c 2010-10-05 03:03:22.880444398 +0200
@@ -29,13 +29,9 @@ static void pci_init(struct device *dev)
uint16_t reg16;
/* Clear system errors */
- reg16 = pci_read_config16(dev, 0x06);
- reg16 |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, reg16);
-
- reg16 = pci_read_config16(dev, 0x1e);
- reg16 |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, reg16);
+ pci_set16(dev, 0x06, 0xf900);
+
+ pci_set16(dev, 0x1e, 0xf800);
}
static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801dx/i82801dx_smihandler.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-7439bd-i82801dx_smihandler.c 2010-10-05 03:03:23.152444072 +0200
@@ -270,9 +270,7 @@ static void busmaster_disable_on_bus(int
continue;
/* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_clear32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -332,9 +330,7 @@ static void southbridge_smi_sleep(unsign
* to "OFF" before entering S5.
*/
if (s5pwr == MAINBOARD_POWER_KEEP) {
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- reg8 |= 1;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+ pci_set8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, 1);
}
/* also iterates over all bridges on bus 0 */
--- src/southbridge/intel/i82801dx/i82801dx_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-0aa12e-i82801dx_pci.c 2010-10-05 03:03:24.120444637 +0200
@@ -29,10 +29,7 @@ static void pci_init(struct device *dev)
/* Enable pci error detecting */
uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* SERR# Enable */
- dword |= (1 << 6); /* Parity Error Response */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 6));
}
static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801ex/i82801ex_lpc.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-f4a23b-i82801ex_lpc.c 2010-10-05 03:03:24.380443784 +0200
@@ -243,12 +243,8 @@ static void lpc_init(struct device *dev)
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */
- value = pci_read_config32(dev, 0xd0);
- value |= (1 << 8)|(1<<7)|(1<<1);
- pci_write_config32(dev, 0xd0, value);
- value = pci_read_config32(dev, 0xd4);
- value |= (1<<1);
- pci_write_config32(dev, 0xd4, value);
+ pci_set32(dev, 0xd0, (1 << 8) | (1 << 7) | (1 << 1));
+ pci_set32(dev, 0xd4, (1 << 1));
setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
@@ -327,14 +323,10 @@ static void i82801ex_lpc_enable_resource
pci_dev_enable_resources(dev);
/* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 4);
- pci_write_config8(dev, 0x44, acpi_cntl);
+ pci_set8(dev, 0x44, (1 << 4));
/* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x5c);
- gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x5c, gpio_cntl);
+ pci_set8(dev, 0x5c, (1 << 4));
}
static struct pci_operations lops_pci = {
--- src/southbridge/intel/i82801ex/i82801ex_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3e82cd-i82801ex_pci.c 2010-10-05 03:03:24.984444686 +0200
@@ -10,9 +10,7 @@ static void pci_init(struct device *dev)
uint16_t word;
/* Clear system errors */
- word = pci_read_config16(dev, 0x06);
- word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
+ pci_set16(dev, 0x06, 0xf900);
#if 0
/* System error enable */
@@ -23,9 +21,7 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x04, dword);
#endif
- word = pci_read_config16(dev, 0x1e);
- word |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, word);
+ pci_set16(dev, 0x1e, 0xf800);
}
static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801ex/i82801ex_watchdog.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-7f0346-i82801ex_watchdog.c 2010-10-05 03:03:25.236445468 +0200
@@ -12,9 +12,7 @@ void watchdog_off(void)
/* turn off the ICH5 watchdog */
dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Get TCO base */
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
/* Disable the watchdog timer */
--- src/southbridge/intel/i82801gx/i82801gx_azalia.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-8eb164-i82801gx_azalia.c 2010-10-05 03:03:25.488443725 +0200
@@ -266,9 +266,7 @@ static void azalia_init(struct device *d
// TODO Actually check if we're AC97 or HDA instead of hardcoding this
// here, in devicetree.cb and/or romstage.c.
- reg8 = pci_read_config8(dev, 0x40);
- reg8 |= (1 << 3); // Clear Clock Detect Bit
- pci_write_config8(dev, 0x40, reg8);
+ pci_set8(dev, 0x40, (1 << 3));
reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); // Enable clock detection
@@ -278,13 +276,9 @@ static void azalia_init(struct device *d
printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
//
- reg8 = pci_read_config8(dev, 0x40); // Audio Control
- reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
- pci_write_config8(dev, 0x40, reg8);
+ pci_set8(dev, 0x40, 1);
- reg8 = pci_read_config8(dev, 0x4d); // Docking Status
- reg8 &= ~(1 << 7); // Docking not supported
- pci_write_config8(dev, 0x4d, reg8);
+ pci_clear8(dev, 0x4d, (1 << 7));
#if 0
/* Set routing pin */
pci_write_config32(dev, 0xf8, 0x0);
--- src/southbridge/intel/i82801gx/i82801gx_watchdog.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-4e9f54-i82801gx_watchdog.c 2010-10-05 03:03:26.032443963 +0200
@@ -33,9 +33,7 @@ void watchdog_off(void)
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
/* Enable I/O space. */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Get TCO base. */
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801gx/i82801gx_pcie.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-d3824a-i82801gx_pcie.c 2010-10-05 03:03:26.284444060 +0200
@@ -31,9 +31,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
/* Enable Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_set32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
@@ -46,14 +44,10 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, 0x3e, reg16);
/* Enable IO xAPIC on this PCIe port */
- reg32 = pci_read_config32(dev, 0xd8);
- reg32 |= (1 << 7);
- pci_write_config32(dev, 0xd8, reg32);
+ pci_set32(dev, 0xd8, (1 << 7));
/* Enable Backbone Clock Gating */
- reg32 = pci_read_config32(dev, 0xe1);
- reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
- pci_write_config32(dev, 0xe1, reg32);
+ pci_set32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
#if CONFIG_MMCONF_SUPPORT
/* Set VC0 transaction class */
@@ -71,9 +65,7 @@ static void pci_init(struct device *dev)
#endif
/* Enable common clock configuration */
// Are there cases when we don't want that?
- reg16 = pci_read_config16(dev, 0x50);
- reg16 |= (1 << 6);
- pci_write_config16(dev, 0x50, reg16);
+ pci_set16(dev, 0x50, (1 << 6));
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
--- src/southbridge/intel/i82801gx/i82801gx_sata.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-39ee02-i82801gx_sata.c 2010-10-05 03:03:26.660443835 +0200
@@ -50,9 +50,7 @@ static void sata_init(struct device *dev
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
/* And without AHCI BAR no memory decoding */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~PCI_COMMAND_MEMORY;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_clear16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
pci_write_config8(dev, 0x09, 0x80);
@@ -120,9 +118,7 @@ static void sata_init(struct device *dev
pci_write_config32(dev, 0x24, 0x00000000);
/* And without AHCI BAR no memory decoding */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~PCI_COMMAND_MEMORY;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_clear16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Native mode capable on both primary and secondary (0xa)
* or'ed with enabled (0x50) = 0xf
@@ -176,9 +172,7 @@ static void sata_init(struct device *dev
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
/* Sata Initialization Register */
- reg32 = pci_read_config32(dev, 0x94);
- reg32 |= (1 << 30); // due to some bug
- pci_write_config32(dev, 0x94, reg32);
+ pci_set32(dev, 0x94, (1 << 30));
}
static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--- src/southbridge/intel/i82801gx/i82801gx_lpc.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-4d4f8f-i82801gx_lpc.c 2010-10-05 03:03:27.136444057 +0200
@@ -273,9 +273,7 @@ static void i82801gx_configure_cstates(d
{
u8 reg8;
- reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
- reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
- pci_write_config8(dev, 0xa9, reg8);
+ pci_set8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2));
// Set Deeper Sleep configuration to recommended values
reg8 = pci_read_config8(dev, 0xaa);
--- src/southbridge/intel/i82801gx/i82801gx_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-b0a77b-i82801gx_pci.c 2010-10-05 03:03:27.844446750 +0200
@@ -30,18 +30,13 @@ static void pci_init(struct device *dev)
u8 reg8;
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_set16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ pci_clear16(dev, BCTRL, ((1 << 0) | (1 << 1)));
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
--- src/southbridge/intel/i82801gx/i82801gx_usb.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-34ef54-i82801gx_usb.c 2010-10-05 03:03:28.096448394 +0200
@@ -39,9 +39,7 @@ static void usb_init(struct device *dev)
pci_write_config8(dev, 0xca, 0x00);
// Yes. Another Erratum
- reg8 = pci_read_config8(dev, 0xca);
- reg8 |= (1 << 0);
- pci_write_config8(dev, 0xca, reg8);
+ pci_set8(dev, 0xca, (1 << 0));
printk(BIOS_DEBUG, "done.\n");
}
--- src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-83ad10-i82801gx_usb_ehci.c 2010-10-05 03:03:28.312444949 +0200
@@ -34,14 +34,9 @@ static void usb_ehci_init(struct device
u8 reg8;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- reg32 = pci_read_config32(dev, 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(dev, 0xdc, reg32);
+ pci_set32(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+
+ pci_set32(dev, 0xdc, (1 << 31) | (1 << 27));
reg32 = pci_read_config32(dev, 0xfc);
reg32 &= ~(3 << 2);
@@ -55,9 +50,7 @@ static void usb_ehci_init(struct device
write32(base + 0x24, reg32);
/* workaround */
- reg8 = pci_read_config8(dev, 0x84);
- reg8 |= (1 << 4);
- pci_write_config8(dev, 0x84, reg8);
+ pci_set8(dev, 0x84, (1 << 4));
printk(BIOS_DEBUG, "done.\n");
}
--- src/southbridge/intel/i82801gx/i82801gx.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-12c78a-i82801gx.c 2010-10-05 03:03:28.548446943 +0200
@@ -28,9 +28,7 @@ void i82801gx_enable(device_t dev)
u32 reg32;
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_set32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
}
struct chip_operations southbridge_intel_i82801gx_ops = {
--- src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-0ceffd-i82801gx_smihandler.c 2010-10-05 03:03:28.724443949 +0200
@@ -263,9 +263,7 @@ static void busmaster_disable_on_bus(int
continue;
/* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_clear32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
--- src/southbridge/intel/esb6300/esb6300_lpc.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-05f5bd-esb6300_lpc.c 2010-10-05 03:03:29.488443816 +0200
@@ -238,10 +238,7 @@ static void lpc_init(struct device *dev)
pci_write_config32(dev, 0x58, 0x00001181);
/* IO APIC initialization */
- value = pci_read_config32(dev, 0xd0);
- value |= (1 << 8)|(1<<7);
- value |= (6 << 0)|(1<<13)|(1<<11);
- pci_write_config32(dev, 0xd0, value);
+ pci_set32(dev, 0xd0, (1 << 8) | (1 << 7) | (6 << 0) | (1 << 13) | (1 << 11));
setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
/* disable reset timer */
@@ -343,14 +340,10 @@ static void esb6300_lpc_enable_resources
pci_dev_enable_resources(dev);
/* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 4);
- pci_write_config8(dev, 0x44, acpi_cntl);
+ pci_set8(dev, 0x44, (1 << 4));
/* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x5c);
- gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x5c, gpio_cntl);
+ pci_set8(dev, 0x5c, (1 << 4));
}
static struct pci_operations lops_pci = {
--- src/southbridge/intel/esb6300/esb6300_pci.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-33667a-esb6300_pci.c 2010-10-05 03:03:29.956446794 +0200
@@ -11,13 +11,9 @@ static void pci_init(struct device *dev)
uint16_t word;
/* Clear system errors */
- word = pci_read_config16(dev, 0x06);
- word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
+ pci_set16(dev, 0x06, 0xf900);
- word = pci_read_config16(dev, 0x1e);
- word |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, word);
+ pci_set16(dev, 0x1e, 0xf800);
}
static struct device_operations pci_ops = {
--- src/southbridge/intel/esb6300/esb6300_pic.c 2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3030e4-esb6300_pic.c 2010-10-05 03:03:30.160444351 +0200
@@ -15,9 +15,7 @@ static void pic_init(struct device *dev)
uint16_t word;
/* Clear system errors */
- word = pci_read_config16(dev, 0x06);
- word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
+ pci_set16(dev, 0x06, 0xf900);
/* enable interrupt lines */
pci_write_config8(dev, 0x3c, 0xff);
--- src/southbridge/broadcom/bcm21000/bcm21000_pcie.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2b6d05-bcm21000_pcie.c 2010-10-05 03:03:30.384446661 +0200
@@ -36,15 +36,10 @@ static void pcie_init(struct device *dev
printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
/* enable MSI on PCIE: */
- msicap = pci_read_config32(dev, 0xa0);
- msicap |= (1<<16); /* enable MSI*/
- pci_write_config32(dev, 0xa0, msicap);
+ pci_set32(dev, 0xa0, (1 << 16));
}
static struct pci_operations lops_pci = {
--- src/southbridge/broadcom/bcm5780/bcm5780_pcie.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d13a97-bcm5780_pcie.c 2010-10-05 03:03:30.620444263 +0200
@@ -16,10 +16,7 @@ static void pcie_init(struct device *dev
uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
}
--- src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d20bc7-bcm5785_early_setup.c 2010-10-05 03:03:30.832444207 +0200
@@ -16,16 +16,10 @@ static void bcm5785_enable_lpc(void)
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
/* LPC Control 0 */
- byte = pci_read_config8(dev, 0x44);
- /* Serial 0 */
- byte |= (1<<6);
- pci_write_config8(dev, 0x44, byte);
+ pci_set8(dev, 0x44, (1 << 6));
/* LPC Control 4 */
- byte = pci_read_config8(dev, 0x48);
- /* superio port 0x2e/4e enable */
- byte |=(1<<1)|(1<<0);
- pci_write_config8(dev, 0x48, byte);
+ pci_set8(dev, 0x48, (1 << 1) | (1 << 0));
}
static void bcm5785_enable_wdt_port_cf9(void)
@@ -163,9 +157,7 @@ static void bcm5785_early_setup(void)
dword |= /* (1<<27)|*/(1<<14); // IDE enable
pci_write_config32(dev, 0x64, dword);
- byte = pci_read_config8(dev, 0x84);
- byte |= (1<<0); // SATA enable
- pci_write_config8(dev, 0x84, byte);
+ pci_set8(dev, 0x84, (1 << 0));
// WDT and cf9 for later in coreboot_ram to call hard_reset
bcm5785_enable_wdt_port_cf9();
@@ -175,30 +167,20 @@ static void bcm5785_early_setup(void)
// IDE related
//F0
- byte = pci_read_config8(dev, 0x4e);
- byte |= (1<<4); //enable IDE ext regs
- pci_write_config8(dev, 0x4e, byte);
+ pci_set8(dev, 0x4e, (1 << 4));
//F1
dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
- byte = pci_read_config8(dev, 0x48);
- byte &= ~1; // disable pri channel
- pci_write_config8(dev, 0x48, byte);
+ pci_clear8(dev, 0x48, 1);
pci_write_config8(dev, 0xb0, 0x01);
pci_write_config8(dev, 0xb2, 0x02);
- byte = pci_read_config8(dev, 0x06);
- byte |= (1<<4); // so b0, b2 can not be changed from now
- pci_write_config8(dev, 0x06, byte);
- byte = pci_read_config8(dev, 0x49);
- byte |= 1; // enable second channel
- pci_write_config8(dev, 0x49, byte);
+ pci_set8(dev, 0x06, (1 << 4));
+ pci_set8(dev, 0x49, 1);
//F2
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
- byte = pci_read_config8(dev, 0x40);
- byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
- pci_write_config8(dev, 0x40, byte);
+ pci_set8(dev, 0x40, (1 << 3) | (1 << 2));
pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
--- src/southbridge/broadcom/bcm5785/bcm5785_usb.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-a915e7-bcm5785_usb.c 2010-10-05 03:03:31.176444750 +0200
@@ -14,9 +14,7 @@ static void usb_init(struct device *dev)
{
uint32_t dword;
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<2)|(1<<1)|(1<<0);
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 2) | (1 << 1) | (1 << 0));
pci_write_config8(dev, 0x41, 0x00); // Serversworks said
--- src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c6c0de-bcm5785_enable_rom.c 2010-10-05 03:03:31.464454519 +0200
@@ -8,7 +8,5 @@ static void bcm5785_enable_rom(void)
addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
/* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr, 0x41);
- byte |= 0x0e;
- pci_write_config8(addr, 0x41, byte);
+ pci_set8(addr, 0x41, 0x0e);
}
--- src/southbridge/broadcom/bcm5785/bcm5785_sata.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-66c2c6-bcm5785_sata.c 2010-10-05 03:03:31.688446517 +0200
@@ -22,9 +22,7 @@ static void sata_init(struct device *dev
int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
- byte = pci_read_config8(dev, 0x78);
- byte |= (1<<7);
- pci_write_config8(dev, 0x78, byte);
+ pci_set8(dev, 0x78, (1 << 7));
res = find_resource(dev, 0x24);
mmio_base = res->base;
--- src/southbridge/nvidia/ck804/ck804_enable_rom.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-4aba10-ck804_enable_rom.c 2010-10-05 03:03:31.964459260 +0200
@@ -19,7 +19,5 @@ static void ck804_enable_rom(void)
addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0);
/* Set the 4MB enable bit. */
- byte = pci_read_config8(addr, 0x88);
- byte |= 0x80;
- pci_write_config8(addr, 0x88, byte);
+ pci_set8(addr, 0x88, 0x80);
}
--- src/southbridge/nvidia/ck804/ck804_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-dfde00-ck804_ide.c 2010-10-05 03:03:32.192460753 +0200
@@ -41,9 +41,7 @@ static void ide_init(struct device *dev)
byte = 0x20; /* Latency: 64 --> 32 */
pci_write_config8(dev, 0xd, byte);
- dword = pci_read_config32(dev, 0xf8);
- dword |= 12;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 12);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
--- src/southbridge/nvidia/ck804/ck804_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c9b565-ck804_lpc.c 2010-10-05 03:03:32.464444184 +0200
@@ -42,17 +42,13 @@ static void lpc_common_init(device_t dev
uint32_t dword;
/* I/O APIC initialization */
- byte = pci_read_config8(dev, 0x74);
- byte |= (1 << 0); /* Enable APIC. */
- pci_write_config8(dev, 0x74, byte);
+ pci_set8(dev, 0x74, (1 << 0));
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
setup_ioapic(dword, 0); // Don't rename IOAPIC ID
#if 1
- dword = pci_read_config32(dev, 0xe4);
- dword |= (1 << 23);
- pci_write_config32(dev, 0xe4, dword);
+ pci_set32(dev, 0xe4, (1 << 23));
#endif
}
@@ -154,9 +150,7 @@ static void lpc_init(device_t dev)
/* Enable Error reporting. */
/* Set up sync flood detected. */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
+ pci_set8(dev, 0x47, (1 << 1));
/* Set up NMI on errors. */
byte = inb(0x70); /* RTC70 */
--- src/southbridge/nvidia/ck804/ck804_pci.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b2ae2c-ck804_pci.c 2010-10-05 03:03:32.940444316 +0200
@@ -17,10 +17,7 @@ static void pci_init(struct device *dev)
device_t pci_domain_dev;
struct resource *mem, *pref;
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* System error enable */
- dword |= (1 << 30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
#if 0
word = pci_read_config16(dev, 0x48);
@@ -30,9 +27,7 @@ static void pci_init(struct device *dev)
#endif
#if 1
- dword = pci_read_config32(dev, 0x4c);
- dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */
- pci_write_config32(dev, 0x4c, dword);
+ pci_set32(dev, 0x4c, 0x00440000);
#endif
pci_domain_dev = dev->bus->dev;
--- src/southbridge/nvidia/ck804/ck804_pcie.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-99595a-ck804_pcie.c 2010-10-05 03:03:33.180445262 +0200
@@ -15,10 +15,7 @@ static void pcie_init(struct device *dev
uint32_t dword;
/* Enable PCI error detecting. */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* System error enable */
- dword |= (1 << 30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
}
static struct pci_operations lops_pci = {
--- src/southbridge/nvidia/ck804/ck804_sata.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9ca8c7-ck804_sata.c 2010-10-05 03:03:33.452445810 +0200
@@ -134,9 +134,7 @@ static void sata_init(struct device *dev
pci_write_config32(dev, 0xe0, dword);
#endif
- dword = pci_read_config32(dev, 0xf8);
- dword |= 2;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 2);
#if CK804_SATA_RESET_FOR_ATAPI
dword = pci_read_config32(dev, 0xac);
--- src/southbridge/nvidia/ck804/ck804_usb2.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-fc41b4-ck804_usb2.c 2010-10-05 03:03:33.796452017 +0200
@@ -13,9 +13,7 @@
static void usb2_init(struct device *dev)
{
uint32_t dword;
- dword = pci_read_config32(dev, 0xf8);
- dword |= 40;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 40);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--- src/southbridge/nvidia/ck804/ck804.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-21a5c5-ck804.c 2010-10-05 03:03:34.004445229 +0200
@@ -141,11 +141,7 @@ void ck804_enable(device_t dev)
return;
if (index == 0) {
- final_reg = pci_read_config32(lpc_dev, 0xe8);
- final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)
- | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)
- | (1 << 18) | (1 << 15));
- pci_write_config32(lpc_dev, 0xe8, final_reg);
+ pci_clear32(lpc_dev, 0xe8, ((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) | (1 << 18) | (1 << 15)));
reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
reg |= (1 << 20);
--- src/southbridge/nvidia/mcp55/mcp55_enable_rom.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-6f865d-mcp55_enable_rom.c 2010-10-05 03:03:34.376454667 +0200
@@ -43,13 +43,7 @@ static void mcp55_enable_rom(void)
#endif
/* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr, 0x88);
- byte |= 0xff; //256K
- pci_write_config8(addr, 0x88, byte);
- byte = pci_read_config8(addr, 0x8c);
- byte |= 0xff; //1M
- pci_write_config8(addr, 0x8c, byte);
- word = pci_read_config16(addr, 0x90);
- word |= 0x7fff; //15M
- pci_write_config16(addr, 0x90, word);
+ pci_set8(addr, 0x88, 0xff);
+ pci_set8(addr, 0x8c, 0xff);
+ pci_set16(addr, 0x90, 0x7fff);
}
--- src/southbridge/nvidia/mcp55/mcp55_ide.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-8f850a-mcp55_ide.c 2010-10-05 03:03:34.612449686 +0200
@@ -60,9 +60,7 @@ static void ide_init(struct device *dev)
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
- dword = pci_read_config32(dev, 0xf8);
- dword |= 12;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 12);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
--- src/southbridge/nvidia/mcp55/mcp55_lpc.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-3341f6-mcp55_lpc.c 2010-10-05 03:03:34.852446114 +0200
@@ -58,9 +58,7 @@ static void lpc_common_init(device_t dev
uint32_t ioapic_base;
/* IO APIC initialization */
- byte = pci_read_config8(dev, 0x74);
- byte |= (1<<0); // enable APIC
- pci_write_config8(dev, 0x74, byte);
+ pci_set8(dev, 0x74, (1 << 0));
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
if (master)
@@ -134,9 +132,7 @@ static void lpc_init(device_t dev)
/* Enable Error reporting */
/* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
+ pci_set8(dev, 0x47, (1 << 1));
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
--- src/southbridge/nvidia/mcp55/mcp55_pci.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-5cc8de-mcp55_pci.c 2010-10-05 03:03:35.520451313 +0200
@@ -38,23 +38,15 @@ static void pci_init(struct device *dev)
struct resource *mem, *pref;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
#if 1
//only need (a01,xx]
- word = pci_read_config16(dev, 0x48);
- word |= (1<<0); /* MRL2MRM */
- word |= (1<<2); /* MR2MRM */
- pci_write_config16(dev, 0x48, word);
+ pci_set16(dev, 0x48, (1 << 0) | (1 << 2));
#endif
#if 1
- dword = pci_read_config32(dev, 0x4c);
- dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
- pci_write_config32(dev, 0x4c, dword);
+ pci_set32(dev, 0x4c, 0x00440000);
#endif
pci_domain_dev = dev->bus->dev;
--- src/southbridge/nvidia/mcp55/mcp55.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-09b6c1-mcp55.c 2010-10-05 03:03:35.852452048 +0200
@@ -210,9 +210,7 @@ void mcp55_enable(device_t dev)
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
- final_reg = pci_read_config32(sm_dev, 0xe8);
- final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
- pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+ pci_clear32(sm_dev, 0xe8, ((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14) | (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15) | (1 << 11) | (1 << 10) | (1 << 9))); //enable all at first
#if 0
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
// reg |= (1<<0);
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d937e6-mcp55_early_setup_car.c 2010-10-05 03:03:36.356444101 +0200
@@ -143,9 +143,7 @@ static void mcp55_early_pcie_setup(unsig
int i;
device_t dev;
dev = PCI_DEV(busnx, devnx+1, 1);
- dword = pci_read_config32(dev, 0xe4);
- dword |= 0x3f0; // disable it at first
- pci_write_config32(dev, 0xe4, dword);
+ pci_set32(dev, 0xe4, 0x3f0);
for(i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -167,9 +165,7 @@ static void mcp55_early_pcie_setup(unsig
// wait 100us
udelay(100);
- dword = pci_read_config32(dev, 0xe4);
- dword &= ~(0x3f0); // enable
- pci_write_config32(dev, 0xe4, dword);
+ pci_clear32(dev, 0xe4, (0x3f0));
// need to wait 100ms
mdelay(100);
--- src/southbridge/nvidia/mcp55/mcp55_pcie.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-6ea02d-mcp55_pcie.c 2010-10-05 03:03:37.948451351 +0200
@@ -35,10 +35,7 @@ static void pcie_init(struct device *dev
uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
+ pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
}
--- src/southbridge/nvidia/mcp55/mcp55_sata.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-106c47-mcp55_sata.c 2010-10-05 03:03:38.364448907 +0200
@@ -62,9 +62,7 @@ static void sata_init(struct device *dev
#endif
pci_write_config32(dev, 0x50, dword);
- dword = pci_read_config32(dev, 0xf8);
- dword |= 2;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 2);
}
--- src/southbridge/nvidia/mcp55/mcp55_usb2.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-0e87c9-mcp55_usb2.c 2010-10-05 03:03:38.676453272 +0200
@@ -34,9 +34,7 @@ extern struct ehci_debug_info dbg_info;
static void usb2_init(struct device *dev)
{
uint32_t dword;
- dword = pci_read_config32(dev, 0xf8);
- dword |= 40;
- pci_write_config32(dev, 0xf8, dword);
+ pci_set32(dev, 0xf8, 40);
}
static void usb2_set_resources(struct device *dev)
--- src/southbridge/nvidia/mcp55/mcp55_azalia.c 2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-fd6031-mcp55_azalia.c 2010-10-05 03:03:38.980450218 +0200
@@ -228,9 +228,7 @@ static void azalia_init(struct device *d
pci_write_config8(dev, 0x3c, 0x0a); // unused?
- reg8 = pci_read_config8(dev, 0x40);
- reg8 |= (1 << 3); // Clear Clock Detect Bit
- pci_write_config8(dev, 0x40, reg8);
+ pci_set8(dev, 0x40, (1 << 3));
reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); // Enable clock detection
@@ -240,13 +238,9 @@ static void azalia_init(struct device *d
printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
//
- reg8 = pci_read_config8(dev, 0x40); // Audio Control
- reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
- pci_write_config8(dev, 0x40, reg8);
+ pci_set8(dev, 0x40, 1);
- reg8 = pci_read_config8(dev, 0x4d); // Docking Status
- reg8 &= ~(1 << 7); // Docking not supported
- pci_write_config8(dev, 0x4d, reg8);
+ pci_clear8(dev, 0x4d, (1 << 7));
res = find_resource(dev, 0x10);
if (!res)
--- src/mainboard/hp/dl145_g3/mptable.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-429b75-mptable.c 2010-10-05 03:03:39.557444053 +0200
@@ -129,9 +129,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 30));
}
// set GEVENT pins to NO OP
outb(0x33, 0xcd6); outb(0x00, 0xcd7);
@@ -145,9 +143,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x205, 0);
if (dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 26));
}
}
--- src/mainboard/hp/dl165_g6_fam10/mptable.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-a39f44-mptable.c 2010-10-05 03:03:40.093443914 +0200
@@ -110,9 +110,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 30));
}
// set GEVENT pins to NO OP
/* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
@@ -126,9 +124,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x205, 0);
if (dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
- pci_write_config32(dev, 0x64, dword);
+ pci_set32(dev, 0x64, (1 << 26));
}
}
--- src/mainboard/amd/dbm690t/mainboard.c 2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-9efd96-mainboard.c 2010-10-05 03:03:40.589443797 +0200
@@ -101,9 +101,7 @@ static void get_ide_dma66(void)
printk(BIOS_INFO, "%s.\n", __func__);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
+ pci_set8(sm_dev, 0xA9, (1 << 5));
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
byte = pci_read_config8(ide_dev, 0x56);
@@ -145,9 +143,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/amd/pistachio/mainboard.c 2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-9d9f69-mainboard.c 2010-10-05 03:03:41.013444592 +0200
@@ -163,19 +163,13 @@ static void set_thermal_config(void)
/* GPM5 as GPIO not USB OC */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword = pci_read_config32(sm_dev, 0x64);
- dword |= 1 << 19;
- pci_write_config32(sm_dev, 0x64, dword);
+ pci_set32(sm_dev, 0x64, 1 << 19);
/* Enable Client Management Index/Data registers */
- dword = pci_read_config32(sm_dev, 0x78);
- dword |= 1 << 11; /* Cms_enable */
- pci_write_config32(sm_dev, 0x78, dword);
+ pci_set32(sm_dev, 0x78, 1 << 11);
/* MiscfuncEnable */
- byte = pci_read_config8(sm_dev, 0x41);
- byte |= (1 << 5);
- pci_write_config8(sm_dev, 0x41, byte);
+ pci_set8(sm_dev, 0x41, (1 << 5));
/* set GPM5 as input */
/* set index register 0C50h to 13h (miscellaneous control) */
@@ -215,9 +209,7 @@ static void set_thermal_config(void)
pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/amd/tilapia_fam10/mainboard.c 2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-6b4283-mainboard.c 2010-10-05 03:03:41.409444072 +0200
@@ -95,10 +95,7 @@ void set_pcie_reset()
/* set the GPIO65 output enable and the value is 0 */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
+ pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
}
#if 0 /* TODO: */
@@ -142,9 +139,7 @@ u8 is_dev3_present(void)
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
+ pci_set16(sm_dev, 0x7e, 1 << 6);
/* read the GPIO68 input status */
word = pci_read_config16(sm_dev, 0x7e);
@@ -204,13 +199,7 @@ static void set_gpio40_gfx(void)
printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
/* when the gpio40 is configured as GPIO, this will enable the output */
pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
+ pci_clear32(sm_dev, 0xfc, ((1 << 10) | (1 << 26)));
}
}
@@ -244,9 +233,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/amd/mahogany/mainboard.c 2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-f9589f-mainboard.c 2010-10-05 03:03:41.797444036 +0200
@@ -59,10 +59,7 @@ void set_pcie_reset()
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
+ pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
}
#if 0 /* not tested yet */
--- src/mainboard/amd/mahogany_fam10/mainboard.c 2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-e49a8d-mainboard.c 2010-10-05 03:03:42.045446539 +0200
@@ -59,10 +59,7 @@ void set_pcie_reset()
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
+ pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
}
#if 0 /* not tested yet. */
--- src/mainboard/msi/ms7135/romstage.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-ac1c37-romstage.c 2010-10-05 03:03:42.289445802 +0200
@@ -99,15 +99,10 @@ static void sio_setup(void)
uint8_t byte;
/* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
+ pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
/* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1 << 0) | (1 << 1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/msi/ms7260/romstage.c 2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-bb1731-romstage.c 2010-10-05 03:03:42.537444376 +0200
@@ -123,17 +123,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/msi/ms9185/mptable.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-61b92d-mptable.c 2010-10-05 03:03:42.853444933 +0200
@@ -122,9 +122,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
- pci_write_config32(dev, 0x6c, dword);
+ pci_set32(dev, 0x6c, (1 << 4));
}
}
--- src/mainboard/msi/ms9282/romstage.c 2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-6f4ffb-romstage.c 2010-10-05 03:03:43.193445295 +0200
@@ -134,9 +134,7 @@ static void sio_setup(void)
byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
--- src/mainboard/msi/ms9652_fam10/romstage.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-033705-romstage.c 2010-10-05 03:03:43.505445181 +0200
@@ -130,9 +130,7 @@ static void sio_setup(void)
byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
}
#include "spd_addr.h"
--- src/mainboard/via/epia/romstage.c 2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-4da27c-romstage.c 2010-10-05 03:03:43.865446726 +0200
@@ -68,10 +68,7 @@ static void enable_shadow_ram(void)
device_t dev = 0;
unsigned char shadowreg;
- shadowreg = pci_read_config8(dev, 0x63);
- /* 0xf0000-0xfffff */
- shadowreg |= 0x30;
- pci_write_config8(dev, 0x63, shadowreg);
+ pci_set8(dev, 0x63, 0x30);
}
static void main(unsigned long bist)
--- src/mainboard/via/epia-m700/romstage.c 2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-bef3cd-romstage.c 2010-10-05 03:03:44.109444668 +0200
@@ -160,9 +160,7 @@ static void enable_shadow_ram(void)
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
/* 0xf0000-0xfffff - ACPI tables */
- shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
- shadowreg |= 0x30;
- pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+ pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
/* 0xe0000-0xeffff - elfload? */
/*
--- src/mainboard/via/epia-m/romstage.c 2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-ea7f2e-romstage.c 2010-10-05 03:03:44.924455417 +0200
@@ -62,10 +62,7 @@ static void enable_shadow_ram(void)
device_t dev = 0; /* no need to look up 0:0.0 */
unsigned char shadowreg;
/* dev 0 for southbridge */
- shadowreg = pci_read_config8(dev, 0x63);
- /* 0xf0000-0xfffff */
- shadowreg |= 0x30;
- pci_write_config8(dev, 0x63, shadowreg);
+ pci_set8(dev, 0x63, 0x30);
}
static void main(unsigned long bist)
--- src/mainboard/via/epia-n/romstage.c 2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-be57a0-romstage.c 2010-10-05 03:03:45.184444652 +0200
@@ -98,10 +98,7 @@ static void enable_shadow_ram(void)
{
unsigned char shadowreg;
- shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
- /* 0xf0000-0xfffff Read/Write*/
- shadowreg |= 0x30;
- pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
+ pci_set8(ctrl.d0f3, 0x82, 0x30);
}
static void main(unsigned long bist)
--- src/mainboard/via/vt8454c/romstage.c 2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-f130f9-romstage.c 2010-10-05 03:03:45.468449238 +0200
@@ -81,9 +81,7 @@ static void enable_shadow_ram(const stru
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
/* 0xf0000-0xfffff - ACPI tables */
- shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
- shadowreg |= 0x30;
- pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+ pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
}
void main(unsigned long bist)
--- src/mainboard/asus/a8n_e/romstage.c 2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-185ca0-romstage.c 2010-10-05 03:03:45.716445191 +0200
@@ -93,14 +93,10 @@ static void sio_setup(void)
uint8_t byte;
/* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
+ pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
/* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/asus/a8v-e_se/romstage.c 2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-2b5a2b-romstage.c 2010-10-05 03:03:46.024445650 +0200
@@ -85,9 +85,7 @@ void soft_reset(void)
print_debug("soft reset \n");
/* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+ pci_set8(PCI_DEV(0, 0x11, 0), 0x4f, 0x01);
while (1) {
/* daisy daisy ... */
--- src/mainboard/asus/m2v-mx_se/romstage.c 2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-4ae108-romstage.c 2010-10-05 03:03:46.392445712 +0200
@@ -115,10 +115,7 @@ void soft_reset(void)
print_debug("soft reset \n");
/* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+ pci_set8(PCI_DEV(0, 0x11, 0), 0x4f, 0x01);
while (1) {
/* daisy daisy ... */
--- src/mainboard/asus/m4a785-m/mainboard.c 2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-f5280f-mainboard.c 2010-10-05 03:03:46.712444476 +0200
@@ -94,10 +94,7 @@ void set_pcie_reset()
/* set the GPIO65 output enable and the value is 0 */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
+ pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
}
#if 0 /* TODO: */
@@ -143,9 +140,7 @@ u8 is_dev3_present(void)
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
+ pci_set16(sm_dev, 0x7e, 1 << 6);
/* read the GPIO68 input status */
word = pci_read_config16(sm_dev, 0x7e);
@@ -189,9 +184,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/dell/s1850/romstage.c 2010-10-01 12:04:15.000000000 +0200
+++ /tmp/cocci-output-5159-a9745f-romstage.c 2010-10-05 03:03:47.088443890 +0200
@@ -188,46 +188,32 @@ static void main(unsigned long bist)
* we're going to clone it.
*/
/* enable a hidden device. */
- b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
- b |= 0x8;
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+ pci_set8(PCI_DEV(0, 0, 0), 0xf4, 0x8);
/* read-write lock in CMOS on LPC bridge on ICH5 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
/* operate on undocumented device */
- l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
- l |= 0x1000;
- pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
-
- l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
- l |= 0x8000;
- pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
+ pci_set32(PCI_DEV(0, 0, 2), 0xa4, 0x1000);
+
+ pci_set32(PCI_DEV(0, 0, 2), 0x9c, 0x8000);
/* disable undocumented device */
- b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
- b &= ~0x8;
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+ pci_clear8(PCI_DEV(0, 0, 0), 0xf4, 0x8);
/* set up LPC bridge bits, some of which reply on undocumented
* registers
*/
- b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
- b |= 4;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
-
- b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
- b |= 2;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
+
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xd4, 2);
/* ACPI base address */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
/* Enable specific ACPI features */
- b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
- b |= 0x10;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0x44, 0x10);
/* ACPI control */
w = inw(0x868);
@@ -248,9 +234,7 @@ static void main(unsigned long bist)
#endif
/* another device enable? */
- b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
- b |= 2;
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+ pci_set8(PCI_DEV(0, 0, 0), 0xf4, 2);
/* ?? */
l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
--- src/mainboard/dell/s1850/watchdog.c 2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-dcd499-watchdog.c 2010-10-05 03:03:47.504444667 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/roda/rk886ex/romstage.c 2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-e3e971-romstage.c 2010-10-05 03:03:47.724443941 +0200
@@ -201,22 +201,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
--- src/mainboard/sunw/ultra40/romstage.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-91b832-romstage.c 2010-10-05 03:03:48.248443877 +0200
@@ -115,9 +115,7 @@ static void sio_setup(void)
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<29)|(1<<0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 29) | (1 << 0));
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
--- src/mainboard/tyan/s2891/romstage.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-8d63d1-romstage.c 2010-10-05 03:03:48.680443992 +0200
@@ -81,23 +81,16 @@ static void sio_setup(void)
uint8_t byte;
/* subject decoding*/
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+ pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
/* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1<<0) | (1<<1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
#if 1
/* s2891 has onboard LPC port 80 */
/*Hope I can enable port 80 here
It will decode port 80 to LPC, If you are using PCI post code you can not do this */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
#endif
}
--- src/mainboard/tyan/s2892/romstage.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-ebff70-romstage.c 2010-10-05 03:03:49.044443866 +0200
@@ -83,13 +83,9 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/tyan/s2895/romstage.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-7b902a-romstage.c 2010-10-05 03:03:49.420444055 +0200
@@ -103,17 +103,11 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<29)|(1<<0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 29) | (1 << 0));
+
+ pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
--- src/mainboard/tyan/s2912/romstage.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-166204-romstage.c 2010-10-05 03:03:49.856444434 +0200
@@ -133,18 +133,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- /*serial 0 */
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/tyan/s2912_fam10/romstage.c 2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-41ee43-romstage.c 2010-10-05 03:03:50.292443864 +0200
@@ -123,18 +123,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- /*serial 0 */
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
#include "spd_addr.h"
--- src/mainboard/arima/hdama/mptable.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-2d9115-mptable.c 2010-10-05 03:03:50.752444024 +0200
@@ -325,9 +325,7 @@ static void reboot_if_hotswap(void)
pci_write_config8(dev, 0x41, 0xf1);
/* reset */
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
- htic = pci_read_config32(dev, HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ pci_clear32(dev, HT_INIT_CONTROL, HTIC_BIOSR_Detect);
outb(0x0e, 0x0cf9);
}
else {
--- src/mainboard/getac/p470/romstage.c 2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-6e087a-romstage.c 2010-10-05 03:03:51.488444034 +0200
@@ -236,22 +236,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
--- src/mainboard/ibase/mb899/romstage.c 2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-74d9db-romstage.c 2010-10-05 03:03:52.300445076 +0200
@@ -198,22 +198,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
--- src/mainboard/intel/d945gclf/romstage.c 2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-71095d-romstage.c 2010-10-05 03:03:52.896444072 +0200
@@ -160,22 +160,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
--- src/mainboard/intel/jarrell/jarrell_fixups.c 2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-46b550-jarrell_fixups.c 2010-10-05 03:03:53.392443835 +0200
@@ -13,9 +13,7 @@ static void mch_reset(void)
base = ICH5_GPIOBASE;
/* Enable GPIO Bar */
- value = pci_read_config32(dev, 0x5c);
- value |= 0x10;
- pci_write_config32(dev, 0x5c, value);
+ pci_set32(dev, 0x5c, 0x10);
/* Set GPIO 19 mux to IO usage */
value = inl(base);
--- src/mainboard/intel/jarrell/watchdog.c 2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-320361-watchdog.c 2010-10-05 03:03:53.800447098 +0200
@@ -26,9 +26,7 @@ static void disable_ich5_watchdog(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
@@ -54,18 +52,14 @@ static void disable_jarell_frb3(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 0);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 0));
/* Set gpio base */
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
base = ICH5_GPIOBASE;
/* Enable GPIO Bar */
- value = pci_read_config32(dev, 0x5c);
- value |= 0x10;
- pci_write_config32(dev, 0x5c, value);
+ pci_set32(dev, 0x5c, 0x10);
/* Configure GPIO 48 and 40 as GPIO */
value = inl(base + 0x30);
@@ -111,9 +105,7 @@ static void ich5_watchdog_on(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/kontron/kt690/mainboard.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-601b65-mainboard.c 2010-10-05 03:03:54.200447019 +0200
@@ -101,9 +101,7 @@ static void get_ide_dma66(void)
printk(BIOS_INFO, "%s.\n", __func__);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
+ pci_set8(sm_dev, 0xA9, (1 << 5));
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
byte = pci_read_config8(ide_dev, 0x56);
@@ -145,9 +143,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/kontron/986lcd-m/romstage.c 2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-2f549d-romstage.c 2010-10-05 03:03:54.552450241 +0200
@@ -288,22 +288,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+ pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-8bfa37-romstage.c 2010-10-05 03:03:55.096446028 +0200
@@ -118,17 +118,11 @@ static void sio_setup(void)
/* set FAN ctrl to DC mode */
smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
--- src/mainboard/supermicro/h8dme/romstage.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-84cc96-romstage.c 2010-10-05 03:03:55.440444280 +0200
@@ -182,17 +182,11 @@ static void sio_setup(void)
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
/* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
--- src/mainboard/supermicro/h8dmr/romstage.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-146759-romstage.c 2010-10-05 03:03:55.852444245 +0200
@@ -126,17 +126,11 @@ static void sio_setup(void)
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/supermicro/x6dai_g/watchdog.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-08a955-watchdog.c 2010-10-05 03:03:56.184447144 +0200
@@ -15,9 +15,7 @@ static void disable_esb6300_watchdog(voi
die("Missing 6300ESB?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/x6dhe_g/watchdog.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-9fdfcc-watchdog.c 2010-10-05 03:03:56.396446359 +0200
@@ -28,9 +28,7 @@ static void disable_esb6300_watchdog(voi
die("Missing esb6300?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
--- src/mainboard/supermicro/x6dhr_ig2/watchdog.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-49e430-watchdog.c 2010-10-05 03:03:56.620445987 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/x6dhe_g2/watchdog.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-e09992-watchdog.c 2010-10-05 03:03:56.836446663 +0200
@@ -28,9 +28,7 @@ static void disable_esb6300_watchdog(voi
die("Missing esb6300?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
--- src/mainboard/supermicro/x6dhr_ig/watchdog.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-5a058b-watchdog.c 2010-10-05 03:03:57.052446427 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
die("Missing ich5?");
}
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_set16(dev, 0x04, (1 << 10));
/* Set and enable acpibase */
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/h8qme_fam10/romstage.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-4ddcaa-romstage.c 2010-10-05 03:03:57.280444624 +0200
@@ -121,17 +121,11 @@ static void sio_setup(void)
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
--- src/mainboard/broadcom/blast/mptable.c 2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-2472ef-mptable.c 2010-10-05 03:03:57.652446216 +0200
@@ -101,9 +101,7 @@ static void *smp_write_config_table(void
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
- pci_write_config32(dev, 0x6c, dword);
+ pci_set32(dev, 0x6c, (1 << 4));
}
--- src/mainboard/jetway/pa78vm5/mainboard.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-75257e-mainboard.c 2010-10-05 03:03:58.064451811 +0200
@@ -61,10 +61,7 @@ void set_pcie_reset()
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
+ pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
}
#if 0 /* not tested yet. */
--- src/mainboard/nvidia/l1_2pvv/romstage.c 2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-3510ec-romstage.c 2010-10-05 03:03:58.360453032 +0200
@@ -137,17 +137,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/technexion/tim5690/tn_post_code.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-2418ee-tn_post_code.c 2010-10-05 03:03:58.748450358 +0200
@@ -67,13 +67,9 @@ void technexion_post_code_init(void)
reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA
pmio_write(0x5e, reg8_data);
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1<<0);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1<<0);
- pci_write_config8(dev, 0xa9, reg8_data);
+ pci_set8(dev, 0xa8, (1 << 0));
+
+ pci_clear8(dev, 0xa9, (1 << 0));
// LED[bit3]:GPIO6
// This is reference SB600 RRG 4.1.1 GPIO
@@ -81,32 +77,20 @@ void technexion_post_code_init(void)
reg8_data |= (1<<7); // 1: GPIO if not used by SATA
pmio_write(0x60, reg8_data);
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1<<2);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1<<2);
- pci_write_config8(dev, 0xa9, reg8_data);
+ pci_set8(dev, 0xa8, (1 << 2));
+
+ pci_clear8(dev, 0xa9, (1 << 2));
// LED[bit4]:GPIO7
// This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1<<3);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1<<3);
- pci_write_config8(dev, 0xa9, reg8_data);
+ pci_set8(dev, 0xa8, (1 << 3));
+
+ pci_clear8(dev, 0xa9, (1 << 3));
// LED[bit5]:GPIO8
// This is reference SB600 RRG 4.1.1 GPIO
- reg8_data = pci_read_config8(dev, 0xa8);
- reg8_data |= (1<<4);
- pci_write_config8(dev, 0xa8, reg8_data);
-
- reg8_data = pci_read_config8(dev, 0xa9);
- reg8_data &= ~(1<<4);
- pci_write_config8(dev, 0xa9, reg8_data);
+ pci_set8(dev, 0xa8, (1 << 4));
+
+ pci_clear8(dev, 0xa9, (1 << 4));
// LED[bit6]:GPIO10
// This is reference SB600 RRG 4.1.1 GPIO
--- src/mainboard/technexion/tim5690/mainboard.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-63c83c-mainboard.c 2010-10-05 03:03:59.085444155 +0200
@@ -143,9 +143,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/technexion/tim8690/mainboard.c 2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-b9e0a6-mainboard.c 2010-10-05 03:03:59.469444833 +0200
@@ -62,18 +62,13 @@ static void enable_onboard_nic(void)
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0x9a);
- byte |= ( 1 << 7);
- pci_write_config8(sm_dev, 0x9a, byte);
+ pci_set8(sm_dev, 0x9a, (1 << 7));
byte=pm_ioread(0x59);
byte &= ~( 1<< 5);
pm_iowrite(0x59,byte);
- byte = pci_read_config8(sm_dev, 0xA8);
-
- byte |= (1 << 1); //set bit 1 to high
- pci_write_config8(sm_dev, 0xA8, byte);
+ pci_set8(sm_dev, 0xA8, (1 << 1));
}
/* set thermal config
@@ -105,9 +100,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-eb5c62-romstage.c 2010-10-05 03:03:59.781444095 +0200
@@ -135,17 +135,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/gigabyte/m57sli/romstage.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-e149a2-romstage.c 2010-10-05 03:04:00.145443945 +0200
@@ -137,17 +137,11 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+ pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/gigabyte/ma78gm/mainboard.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-d453a7-mainboard.c 2010-10-05 03:04:00.521446761 +0200
@@ -60,10 +60,7 @@ void set_pcie_reset()
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
+ pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
}
--- src/mainboard/gigabyte/ma785gmt/mainboard.c 2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-310315-mainboard.c 2010-10-05 03:04:00.793446056 +0200
@@ -95,10 +95,7 @@ void set_pcie_reset()
/* set the GPIO65 output enable and the value is 0 */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
+ pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
}
@@ -115,9 +112,7 @@ int is_dev3_present(void)
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
+ pci_set16(sm_dev, 0x7e, 1 << 6);
/* read the GPIO68 input status */
word = pci_read_config16(sm_dev, 0x7e);
@@ -178,13 +173,7 @@ static void set_gpio40_gfx(void)
printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
/* when the gpio40 is configured as GPIO, this will enable the output */
pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
+ pci_clear32(sm_dev, 0xfc, ((1 << 10) | (1 << 26)));
}
}
@@ -218,9 +207,7 @@ static void set_thermal_config(void)
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
+ pci_set16(sm_dev, 0x56, 1 << 7);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
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