[coreboot] [commit] r5912 - in trunk/src: mainboard/asus/a8n_e mainboard/gigabyte/m57sli mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv main...
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svn at coreboot.org
Tue Oct 5 19:59:12 CEST 2010
Author: myles
Date: Tue Oct 5 19:59:12 2010
New Revision: 5912
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5912
Log:
attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.
Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Pter Stuge <peter at stuge.se>
Modified:
trunk/src/mainboard/asus/a8n_e/romstage.c
trunk/src/mainboard/gigabyte/m57sli/Kconfig
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/msi/ms7135/Kconfig
trunk/src/mainboard/msi/ms7135/romstage.c
trunk/src/mainboard/msi/ms7260/Kconfig
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/Kconfig
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/sunw/ultra40/Kconfig
trunk/src/mainboard/sunw/ultra40/romstage.c
trunk/src/mainboard/supermicro/h8dme/Kconfig
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/Kconfig
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
trunk/src/mainboard/tyan/s2895/romstage.c
trunk/src/mainboard/tyan/s2912/Kconfig
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/Kconfig
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/southbridge/nvidia/ck804/Kconfig
trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
trunk/src/southbridge/nvidia/mcp55/Kconfig
trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -42,10 +42,6 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
-
-/* Used by ck894_early_setup(). */
-#define CK804_NUM 1
-
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -8,6 +8,8 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_ITE_IT8716F
select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
select HAVE_BUS_CONFIG
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -90,10 +90,6 @@
return smbus_read_byte(device, address);
}
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 0
#define MCP55_MB_SETUP \
Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms7135/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -15,6 +15,8 @@
select HAVE_MP_TABLE
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
+ select CK804_USE_NIC
+ select CK804_USE_ACI
config MAINBOARD_DIR
string
Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -43,10 +43,6 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-/* Used by ck804_early_setup(). */
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms7260/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -8,6 +8,8 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -92,9 +92,6 @@
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
#define MCP55_PCI_E_X_0 0
#define MCP55_MB_SETUP \
Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms9282/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -105,7 +105,6 @@
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
//set GPIO to input mode
#define MCP55_MB_SETUP \
Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -8,6 +8,8 @@
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -89,10 +89,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 1
#define MCP55_MB_SETUP \
Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -9,6 +9,8 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
@@ -44,6 +46,10 @@
int
default 1
+config MCP55_NUM
+ int
+ default 2
+
config SB_HT_CHAIN_ON_BUS0
int
default 2
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -100,10 +100,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 2
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 2
#define MCP55_PCI_E_X_1 4
Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -14,6 +14,8 @@
select HAVE_MP_TABLE
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_1024
+ select CK804_USE_NIC
+ select CK804_USE_ACI
config MAINBOARD_DIR
string
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -78,9 +78,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -9,6 +9,8 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627HF
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -155,10 +155,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 4
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -9,6 +9,8 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627HF
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -100,10 +100,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 4
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -8,6 +8,8 @@
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -89,10 +89,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 4
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -92,10 +92,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 0
-#define MCP55_USE_AZA 0
-
#define MCP55_PCI_E_X_0 4
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -62,12 +62,9 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_NUM 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -72,9 +72,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2912/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -9,6 +9,7 @@
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -100,9 +100,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-
#define MCP55_PCI_E_X_0 1
#define MCP55_MB_SETUP \
Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -8,6 +8,7 @@
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -89,9 +89,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-
#define MCP55_PCI_E_X_0 1
#define MCP55_MB_SETUP \
Modified: trunk/src/southbridge/nvidia/ck804/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -16,3 +16,14 @@
hex
default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
+config CK804_USE_NIC
+ bool
+ default n if SOUTHBRIDGE_NVIDIA_CK804
+
+config CK804_USE_ACI
+ bool
+ default n if SOUTHBRIDGE_NVIDIA_CK804
+
+config CK804_NUM
+ int
+ default 1 if SOUTHBRIDGE_NVIDIA_CK804
Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -52,7 +52,7 @@
#define CK804_PCI_E_X 4
#endif
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
#ifndef CK804B_BUSN
@@ -63,14 +63,6 @@
#endif
#endif
-#ifndef CK804_USE_NIC
-#define CK804_USE_NIC 0
-#endif
-
-#ifndef CK804_USE_ACI
-#define CK804_USE_ACI 0
-#endif
-
#define CK804_CHIP_REV 3
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
@@ -89,12 +81,12 @@
{
static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
#endif
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
#endif
};
@@ -106,11 +98,11 @@
{
static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
#endif
PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
#endif
};
@@ -126,7 +118,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
@@ -141,7 +133,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
@@ -155,7 +147,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
#endif
@@ -164,7 +156,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
@@ -173,7 +165,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
@@ -190,7 +182,7 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
@@ -200,7 +192,7 @@
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
#endif
@@ -226,7 +218,7 @@
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
@@ -240,25 +232,25 @@
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
#endif
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -266,17 +258,17 @@
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
#endif
-#if CK804_USE_ACI == 1
+#if CONFIG_CK804_USE_ACI
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
#endif
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
#endif
-#if CK804_NUM > 1
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_NUM > 1
+#if CONFIG_CK804_USE_NIC
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -296,7 +288,7 @@
setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -55,14 +55,6 @@
#define CK804B_PCI_E_X 4
#endif
-#ifndef CK804_USE_NIC
-#define CK804_USE_NIC 0
-#endif
-
-#ifndef CK804_USE_ACI
-#define CK804_USE_ACI 0
-#endif
-
#define CK804_CHIP_REV 3
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
@@ -198,7 +190,7 @@
//SYSCTRL
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -206,7 +198,7 @@
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23),
#endif
-#if CK804_USE_ACI == 1
+#if CONFIG_CK804_USE_ACI
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
#endif
@@ -271,7 +263,7 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 19:59:12 2010 (r5912)
@@ -1,7 +1,7 @@
config SOUTHBRIDGE_NVIDIA_MCP55
bool
- select IOAPIC
select HAVE_USBDEBUG
+ select IOAPIC
config ID_SECTION_OFFSET
hex
@@ -15,3 +15,14 @@
hex
default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+config MCP55_USE_NIC
+ bool
+ default n if SOUTHBRIDGE_NVIDIA_MCP55
+
+config MCP55_USE_AZA
+ bool
+ default n if SOUTHBRIDGE_NVIDIA_MCP55
+
+config MCP55_NUM
+ int
+ default 1 if SOUTHBRIDGE_NVIDIA_MCP55
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Oct 5 15:40:31 2010 (r5911)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Oct 5 19:59:12 2010 (r5912)
@@ -89,14 +89,6 @@
#define MCP55_PCI_E_X_3 4
#endif
-#ifndef MCP55_USE_NIC
- #define MCP55_USE_NIC 0
-#endif
-
-#ifndef MCP55_USE_AZA
- #define MCP55_USE_AZA 0
-#endif
-
#define MCP55_CHIP_REV 3
static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
@@ -269,7 +261,7 @@
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-#if MCP55_USE_AZA == 1
+#if CONFIG_MCP55_USE_AZA
RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
@@ -279,7 +271,7 @@
MCP55_MB_SETUP
#endif
-#if MCP55_USE_AZA == 1
+#if CONFIG_MCP55_USE_AZA
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
@@ -308,7 +300,7 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
-#if MCP55_USE_NIC == 1
+#if CONFIG_MCP55_USE_NIC
RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
@@ -399,7 +391,7 @@
devn[mcp55_num] = devnx;
io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
mcp55_num++;
- if(mcp55_num == MCP55_NUM) goto out;
+ if(mcp55_num == CONFIG_MCP55_NUM) goto out;
break; // only one MCP55 on one chain
}
}
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