[coreboot] [commit] r5761 - trunk/util/inteltool

repository service svn at coreboot.org
Wed Sep 1 05:40:57 CEST 2010


Author: cozzie
Date: Wed Sep  1 05:40:57 2010
New Revision: 5761
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5761

Log:
Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
Acked-by: Corey Osgood <corey.osgood at gmail.com>

Modified:
   trunk/util/inteltool/gpio.c

Modified: trunk/util/inteltool/gpio.c
==============================================================================
--- trunk/util/inteltool/gpio.c	Tue Aug 31 21:19:16 2010	(r5760)
+++ trunk/util/inteltool/gpio.c	Wed Sep  1 05:40:57 2010	(r5761)
@@ -152,6 +152,41 @@
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich10_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "RESERVED" },
+	{ 0x40, 4, "GPIO_USE_SEL3" },
+	{ 0x44, 4, "GPIO_SEL3" },
+	{ 0x48, 4, "GPIO_LVL3" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 4, "RESERVED" },
+	{ 0x54, 4, "RESERVED" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	{ 0x60, 4, "GP_RST_SEL" },
+	{ 0x64, 4, "RESERVED" },
+	{ 0x68, 4, "RESERVED" },
+	{ 0x6c, 4, "RESERVED" },
+	{ 0x70, 4, "RESERVED" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 int print_gpios(struct pci_dev *sb)
 {
 	int i, size;
@@ -161,6 +196,11 @@
 	printf("\n============= GPIOS =============\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_ICH10R:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich10_gpio_registers;
+		size = ARRAY_SIZE(ich10_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH9DH:
 	case PCI_DEVICE_ID_INTEL_ICH9DO:
 	case PCI_DEVICE_ID_INTEL_ICH9R:




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