[coreboot] [PATCH] fix 'AMD Fam10 code breaks with gcc 4.5.0'

[Paul Menzel]

Dear Scott,


Am Donnerstag, den 02.09.2010, 00:40 -0500 schrieb Scott:

> The subversion comment for -r 5571 states:
> 
>    The AMD Fam10 code breaks with coreboot 4.5.0.
>    Potentially caused by reordering. Going back to 4.4.4
>    which is known working on Fam10 until gcc or the Fam10 code is fixed.
> 
>    Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>    Acked-by: Stefan Reinauer <stepan at coresystems.de>
> 
> 
> I encountered the same problem and debugged it. The AP code that disables
> cache as ram before the final halt has to be all inline. Function calls
> require a valid stack, and the stack is kept in the very cache as ram that
> the code is disabling. I found with gcc 450, the code for rdmsr, disable_cache,
> and enable_cache and not getting inlined as intended. Function calls are

s/and/are/

> generated, and the first one after the AP clears msr 268 fails. The solution
> is to force these functions to generate inline code by adding
> __attribute__((always_inline)) to their declarations:

great find!!! Could you please send a patch according to the development
guidelines. Especially do not forget to add your Signed-off-by line.

Just to leave no doubt, could you please add that you tested your fix
using GCC 4.5.0 with the used hardware.

[…]


Thanks,

Paul
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