[coreboot] [PATCH 3/4] Reduce TSC calibrations from 20ms to 2ms.
Kevin O'Connor
kevin at koconnor.net
Tue Sep 7 01:24:11 CEST 2010
2ms is enough time to accurately obtain the clock rate.
Signed-off-by: Kevin O'Connor <kevin at koconnor.net>
---
src/cpu/x86/tsc/delay_tsc.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 27c89e3..1127867 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -18,8 +18,8 @@ static unsigned long clocks_per_usec;
* device.
*/
-#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
-#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
+#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */
+#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */
static unsigned long long calibrate_tsc(void)
{
--
1.7.2.2
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