[coreboot] [commit] r5810 - in trunk/src: cpu/amd/car cpu/amd/model_10xxx southbridge/nvidia/mcp55
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Mon Sep 13 17:11:36 CEST 2010
Author: myles
Date: Mon Sep 13 17:11:35 2010
New Revision: 5810
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5810
Log:
Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
to make sure MMCONF is set up before use. Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).
This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch at numascale.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Modified:
trunk/src/cpu/amd/car/cache_as_ram.inc
trunk/src/cpu/amd/model_10xxx/init_cpus.c
trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc Mon Sep 13 16:51:26 2010 (r5809)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc Mon Sep 13 17:11:35 2010 (r5810)
@@ -27,6 +27,7 @@
/* for CAR with FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
+#define MSR_MCFG_BASE 0xC0010058
#define MSR_FAM10 0xC001102A
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
@@ -115,7 +116,7 @@
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled
*/
- movl $0xc001102a, %ecx
+ movl $MSR_FAM10, %ecx
rdmsr
bts $15, %eax
wrmsr
@@ -136,6 +137,19 @@
/* Erratum 343 end */
+#if defined(CONFIG_MMCONF_SUPPORT)
+ /* Set MMIO Config space BAR */
+ movl $MSR_MCFG_BASE, %ecx
+ rdmsr
+
+ andl $(~(0xfff00000 | (0xf << 2))), %eax
+ orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax
+ andl $(~(0x0000ffff)), %edx
+ orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
+
+ wrmsr
+#endif
+
CAR_FAM10_out_post_errata:
/* Set MtrrFixDramModEn for clear fixed mtrr */
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c Mon Sep 13 16:51:26 2010 (r5809)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Mon Sep 13 17:11:35 2010 (r5810)
@@ -58,30 +58,6 @@
#endif
-#define _ULLx(x) x ## ULL
-#define _ULL(x) _ULLx(x)
-
-/*[63:0] */
-#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS)
-
-static void set_pci_mmio_conf_reg(void)
-{
-#if CONFIG_MMCONF_SUPPORT
-# if PCI_MMIO_BASE > 0xffffffff
-# error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits!
-# endif
- msr_t msr;
- msr = rdmsr(0xc0010058);
- msr.lo &= ~(0xfff00000 | (0xf << 2));
- // 256 buses, one segment. Total 256M address space.
- msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0);
- msr.hi &= ~(0x0000ffff);
- msr.hi |= (PCI_MMIO_BASE >> (32));
-
- wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
-#endif
-}
-
typedef void (*process_ap_t) (u32 apicid, void *gp);
//core_range = 0 : all cores
@@ -295,9 +271,6 @@
* already set early mtrr in cache_as_ram.inc
*/
- /* enable access pci conf via mmio */
- set_pci_mmio_conf_reg();
-
/* that is from initial apicid, we need nodeid and coreid
later */
id = get_node_core_id_x();
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Mon Sep 13 16:51:26 2010 (r5809)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Mon Sep 13 17:11:35 2010 (r5810)
@@ -267,13 +267,7 @@
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
- /* The following operation hangs when performed via MMCFG:
- pci_read_config32(romcc): 00010000:0078: 20040000
- setup_resource_map_x_offset: 10000, 78: 20040000
- pci_write_config32(romcc): 00010000:0078: 19040000
- (hang)
- Response missing? */
- /* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
+ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
#if MCP55_USE_AZA == 1
RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
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