[coreboot] coreboot and win7
Scott Duplichan
scott at notabs.org
Tue Sep 14 23:38:43 CEST 2010
]-----Original Message-----
]From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Myles Watson
]Sent: Monday, September 13, 2010 09:39 PM
]To: Scott Duplichan
]Cc: coreboot at coreboot.org
]Subject: Re: [coreboot] coreboot and win7
]
]On Mon, Sep 13, 2010 at 5:37 PM, Scott Duplichan <scott at notabs.org> wrote:
]> I am able to boot Win7 using coreboot+seabios on a couple of AMD SB700 systems.
]> Testing so far is with simnow only. Hopefully someone else can try the changes
]> on a real board. I am still building with UMA disabled and using external PCI
]> video instead, to avoid a payload/acpi table overlap problem.
]Thanks for your work.
]
]I'd be interested in your tests of the latest code with the changes to
]the Asus M4... board.
]
]> I have tested
]> with Tilapia family 10h and Mahogany family 10h on simnow using Win7 PE
]> edition (see attached). Usually a pass with this setup means real hardware
]> will work, and other Win7 editions will work as well. Here are the changes:
]>
]> 1) Fix BSOD about "this bios is not fully acpi compliant". Windows makes this
]> BSOD because DRAM is reported both by E820 and by SB ACPI _CRS. Also, there
]> is a reference to undefined ACPI object TOM2. Removing the reporting of DRAM
]> from ACPI _CRS solves these problems.
]>
]> 2) SB I/O APIC ID: Coreboot programs ID zero, which conflicts with processor
]> cores. ACPI reports ID 2, which conflicts with processor cores. Win7
]> reprograms to match ACPI. The conflict seems harmless, at least with simnow
]> testing. I gave the I/O APIC a unique ID just to be sure.
]>
]> 3) PS/2 KB and mouse were missing from ACPI which causes Win7 to ignore them.
]> I added them.
]>
]> Other patches I used, unrelated to Win7:
]>
]> 1) Avoid an essentially infinite PCI bus scan when a bad dev_fn value is
]> passed in from hypertransport.c. It is not clear if this can happen only
]> on simnow.
]This has been patched in svn now. The root cause should still be
]fixed, but at least it shouldn't have an infinite loop any more.
Ah yes, great!
]Thanks,
]Myles
Here is an acpi patch that lets asustek m4a785-m boot win7. It is
tested on simnow with the PE edition of win7. I didn't encounter
any uma-payload overlap problem, so I left uma enabled. However,
simnow doesn't emulate uma graphics for rs780, so I tested using
a pci video card:
Signed-off-by: Scott Duplichan <scott at notabs.org>
Index: src/mainboard/asus/m4a785-m/Kconfig
===================================================================
--- src/mainboard/asus/m4a785-m/Kconfig (revision 5814)
+++ src/mainboard/asus/m4a785-m/Kconfig (working copy)
@@ -21,7 +21,7 @@
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
- select GENERATE_ACPI_TABLES
+ select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select TINY_BOOTBLOCK
Index: src/mainboard/asus/m4a785-m/dsdt.asl
===================================================================
--- src/mainboard/asus/m4a785-m/dsdt.asl (revision 5814)
+++ src/mainboard/asus/m4a785-m/dsdt.asl (working copy)
@@ -22,8 +22,8 @@
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "TILAPIA ", /* TABLE ID */
+ "ASUS ", /* OEMID */
+ "M4A785-M", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
@@ -33,8 +33,6 @@
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
@@ -1167,8 +1165,6 @@
/* _SB.PCI0 */
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
- External (TOM1)
- External (TOM2)
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
@@ -1390,6 +1386,63 @@
})
} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CID, EisaId ("PNP030B"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+
Device(PIC) {
Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
Name(_CRS, ResourceTemplate() {
@@ -1544,48 +1597,11 @@
0xF300 /* length */
)
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
@@ -1593,41 +1609,12 @@
CreateDWordField(CRES, ^EMM1._BAS, EM1B)
CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
If(LGreater(LOMH, 0xC0000)){
Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
}
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
Index: src/northbridge/amd/amdfam10/amdfam10_acpi.c
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10_acpi.c (revision 5814)
+++ src/northbridge/amd/amdfam10/amdfam10_acpi.c (working copy)
@@ -195,7 +195,6 @@
int i;
u32 dword;
- msr_t msr;
// the offset could be different if have different HC_NUMS, and HC_POSSIBLE_NUM and ssdt.asl
BUSN = ssdt+0x3b; //+5 will be next BUSN
@@ -231,9 +230,6 @@
*SBLK = (u8)(sysconf.sblk);
- msr = rdmsr(TOP_MEM);
- int_to_stream(msr.lo, TOM1);
-
int_to_stream(sysconf.sbdn, SBDN);
for(i=0;i<sysconf.hc_possible_num;i++) {
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