[coreboot] Super I/O: Winbond LPC Super I/O WPCN381U

[Corey Osgood]

On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles <cubicool at gmail.com> wrote:
> On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote:
>> Jeremy Moles wrote:
>> > > To clarify, superiotool has functions internally for writing to
>> > > registers in superios,
>> ..
>> > I will need to find whatever register corresponds to GPIO03 and
>> > set just that particular HIGH bit?
>>
>> Yes. Look at the data sheet and maybe as a help you can step through
>> superiotool as well.
>>
>>
>> > (Other keywords in their email were things like "GPIO:0x2" and
>> > GPIO:0x18", but I haven't been able to get any additional
>> > clarification from them...)
>>
>> Superios are easier to program than many other components, and are
>> well documented, so you shouldn't have too much trouble. GPIO 3 is
>> what you need to know about how the hardware is built.
>
> I do have a document describing the hardware pretty thoroughly, but
> I am unfamiliar with the terminology it uses and how I would map that
> into something I AM familiar with in Linux.
>
> When you say well-documented: is there a particular document you can
> think of offhand?
>
> At any rate, I'm sure I'm close to the edge of how much this list is
> willing to tolerate. :) Thanks for the help, hopefully I can make
> something out of this...

Perhaps this will help:

http://www.coreboot.org/Developer_Manual/Super_IO

Try looking at a datasheet for just about any Winbond super IO that
does have a public datasheet, they all work generally the same way,
just the LDNs and registers vary.

Also, have you tried contacting Winbond/Nuvoton for the datasheet?
I've never had them deny me a datasheet, and never had to sign an NDA
for one either. And have you inspected the board to find the Super IO
and confirm that it is a Winbond? Sometimes designs change, it
wouldn't surprise me to find that it really is the NSC chip.

-Corey