[coreboot] Issues porting the Iwave raibowG6
Den nis
dnns187 at gmail.com
Tue Apr 26 16:40:16 CEST 2011
Hi,
Im trying to "port" the iwave RainbowG6 coreboot code to a platform with the
same CPU (Intel Atom Z530) and chipset (Intel US15W), 1GB RAM (2 ranks, 1024
Mbits device density, x16 device width) and a winbond WPCN381U superio chip.
Meanwhile the basic functionalities of Coreboot seems to works well. But
when i jump to my payload everthing become quiet.
I suspect that something went wrong with the tables.
I have include the build process and the serial port output (debug level =
SPEW).
I hope someone has a tip so I can go further.
Many thanks in advance!
Dennis
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coreboot-4.0-r17:52M-Mdl Tue Apr 26 16:29:37 CEST 2011 starting...
US15W Chipset
Unknown (07)Setting up ACPI PM1 block Setting up ACPI P block done.
Setting up RAM controller.
Setting up RAM
Setting up RAM
copy done copy 2 done CPU ID: 67266.
Physical Address size: 32.
Virtual Address size: 32.
1 2 E000/F000 Routing Reserved done.
Loading image.
Check CBFS header at fffffd3e
magic is 4f524243
Found CBFS header at fffffd3e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 33e6 + align -> fff03440
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r17:52M-Mdl Tue Apr 26 16:29:37 CEST 2011 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1e.1: enabled 1
PCI: 00:1e.2: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 164e.2: enabled 1
PNP: 164e.3: enabled 1
PNP: 164e.7: enabled 1
PCI: 00:1f.1: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1e.1: enabled 1
PCI: 00:1e.2: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 164e.2: enabled 1
PNP: 164e.3: enabled 1
PNP: 164e.7: enabled 1
PCI: 00:1f.1: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/8100] ops
PCI: 00:00.0 [8086/8100] enabled
PCI: 00:02.0 [8086/8108] ops
PCI: 00:02.0 [8086/8108] enabled
PCI: 00:1a.0 [8086/8118] ops
PCI: 00:1a.0 [8086/8118] enabled
PCI: 00:1b.0 [8086/811b] ops
PCI: 00:1b.0 [8086/811b] enabled
PCI: 00:1c.0 [8086/8110] bus ops
PCI: 00:1c.0 [8086/8110] enabled
PCI: 00:1c.1 [8086/8112] bus ops
PCI: 00:1c.1 [8086/8112] enabled
PCI: 00:1d.0 [8086/8114] ops
PCI: 00:1d.0 [8086/8114] enabled
PCI: 00:1d.1 [8086/8115] ops
PCI: 00:1d.1 [8086/8115] enabled
PCI: 00:1d.2 [8086/8116] ops
PCI: 00:1d.2 [8086/8116] enabled
PCI: 00:1d.7 [8086/8117] ops
PCI: 00:1d.7 [8086/8117] enabled
PCI: 00:1e.0 [8086/811c] ops
PCI: 00:1e.0 [8086/811c] enabled
PCI: 00:1e.1 [8086/811d] ops
PCI: 00:1e.1 [8086/811d] enabled
PCI: 00:1e.2 [8086/811e] ops
PCI: 00:1e.2 [8086/811e] enabled
PCI: 00:1f.0 [8086/8119] bus ops
PCI: 00:1f.0 [8086/8119] enabled
PCI: 00:1f.1 [8086/811a] ops
PCI: 00:1f.1 [8086/811a] enabled
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
PCI: Using configuration type 1
PCI: 01:00.0 [10ec/8168] enabled
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:1c.1
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
PNP: 164e.2 enabled
PNP: 164e.3 enabled
PNP: 164e.7 enabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=002
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000.
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.1 read_resources bus 2 link: 0
PCI: 00:1c.1 read_resources bus 2 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 164e.2 missing read_resources
PNP: 164e.7 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10
PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 200 index 18
PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c
PCI: 00:1a.0
PCI: 00:1a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 20
PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 00:1c.1
PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:1d.0
PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1d.1
PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1d.2
PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1d.7
PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1e.0
PCI: 00:1e.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:1e.1
PCI: 00:1e.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:1e.2
PCI: 00:1e.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:1f.0 child on link 0 PNP: 164e.2
PCI: 00:1f.0 resource base 0 size e000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 164e.2
PNP: 164e.2 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 164e.2 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 164e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index f1
PNP: 164e.3
PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 3ff flags c0000100 index 60
PNP: 164e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 164e.7
PNP: 164e.7 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 164e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PCI: 00:1f.1
PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 10 * [0x0 - 0xff] io
PCI: 00:1c.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 1c * [0x0 - 0xfff] io
PCI: 00:1d.0 20 * [0x1000 - 0x101f] io
PCI: 00:1d.1 20 * [0x1020 - 0x103f] io
PCI: 00:1d.2 20 * [0x1040 - 0x105f] io
PCI: 00:1f.1 20 * [0x1060 - 0x106f] io
PCI: 00:02.0 14 * [0x1070 - 0x1077] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 20 * [0x0 - 0xffff] prefmem
PCI: 01:00.0 18 * [0x10000 - 0x10fff] prefmem
PCI: 00:1c.0 compute_resources_prefmem: base: 11000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 30 * [0x0 - 0xffff] mem
PCI: 00:1c.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 * [0x0 - 0xfffffff] mem
PCI: 00:1c.0 24 * [0x10000000 - 0x100fffff] prefmem
PCI: 00:1c.0 20 * [0x10100000 - 0x101fffff] mem
PCI: 00:02.0 10 * [0x10200000 - 0x1027ffff] mem
PCI: 00:02.0 1c * [0x10280000 - 0x102bffff] mem
PCI: 00:1b.0 10 * [0x102c0000 - 0x102c3fff] mem
PCI: 00:1a.0 10 * [0x102c4000 - 0x102c4fff] mem
PCI: 00:1d.7 10 * [0x102c5000 - 0x102c53ff] mem
PCI: 00:1e.0 10 * [0x102c5400 - 0x102c54ff] mem
PCI: 00:1e.1 10 * [0x102c5500 - 0x102c55ff] mem
PCI: 00:1e.2 10 * [0x102c5600 - 0x102c56ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 102c5700 size: 102c5700 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:1a.0
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:1c.1
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1d.1
constrain_resources: PCI: 00:1d.2
constrain_resources: PCI: 00:1d.7
constrain_resources: PCI: 00:1e.0
constrain_resources: PCI: 00:1e.1
constrain_resources: PCI: 00:1e.2
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 164e.2
skipping PNP: 164e.2 at 60 fixed resource, size=0!
skipping PNP: 164e.2 at 70 fixed resource, size=0!
skipping PNP: 164e.2 at f1 fixed resource, size=0!
constrain_resources: PNP: 164e.3
constrain_resources: PNP: 164e.7
skipping PNP: 164e.7 at 62 fixed resource, size=0!
skipping PNP: 164e.7 at 70 fixed resource, size=0!
constrain_resources: PCI: 00:1f.1
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 0000e000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:e000 size:1078 align:12 gran:0 limit:ffff
Assigned: PCI: 00:1c.0 1c * [0xe000 - 0xefff] io
Assigned: PCI: 00:1d.0 20 * [0xf000 - 0xf01f] io
Assigned: PCI: 00:1d.1 20 * [0xf020 - 0xf03f] io
Assigned: PCI: 00:1d.2 20 * [0xf040 - 0xf05f] io
Assigned: PCI: 00:1f.1 20 * [0xf060 - 0xf06f] io
Assigned: PCI: 00:02.0 14 * [0xf070 - 0xf077] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: f078 size: 1078 align: 12 gran: 0 done
PCI: 00:1c.0 allocate_resources_io: base:e000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:00.0 10 * [0xe000 - 0xe0ff] io
PCI: 00:1c.0 allocate_resources_io: next_base: e100 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:102c5700 align:28 gran:0 limit:dfffffff
Assigned: PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] mem
Assigned: PCI: 00:1c.0 24 * [0xd0000000 - 0xd00fffff] prefmem
Assigned: PCI: 00:1c.0 20 * [0xd0100000 - 0xd01fffff] mem
Assigned: PCI: 00:02.0 10 * [0xd0200000 - 0xd027ffff] mem
Assigned: PCI: 00:02.0 1c * [0xd0280000 - 0xd02bffff] mem
Assigned: PCI: 00:1b.0 10 * [0xd02c0000 - 0xd02c3fff] mem
Assigned: PCI: 00:1a.0 10 * [0xd02c4000 - 0xd02c4fff] mem
Assigned: PCI: 00:1d.7 10 * [0xd02c5000 - 0xd02c53ff] mem
Assigned: PCI: 00:1e.0 10 * [0xd02c5400 - 0xd02c54ff] mem
Assigned: PCI: 00:1e.1 10 * [0xd02c5500 - 0xd02c55ff] mem
Assigned: PCI: 00:1e.2 10 * [0xd02c5600 - 0xd02c56ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: d02c5700 size: 102c5700 align: 28 gran: 0 done
PCI: 00:1c.0 allocate_resources_prefmem: base:d0000000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 01:00.0 20 * [0xd0000000 - 0xd000ffff] prefmem
Assigned: PCI: 01:00.0 18 * [0xd0010000 - 0xd0010fff] prefmem
PCI: 00:1c.0 allocate_resources_prefmem: next_base: d0011000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: base:d0100000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 01:00.0 30 * [0xd0100000 - 0xd010ffff] mem
PCI: 00:1c.0 allocate_resources_mem: next_base: d0110000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.1 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.1 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
pci_tolm: 0xc0000000
Base of stolen memory: 0x3f800000
Top of Low Used DRAM: 0x00000000
IGD decoded, subtracting 0M UMA
Available memory: 0K (0M)
Adding UMA memory area
Adding PCIe config bar
Adding CMC shadow area
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x00 mem<mmconfig>
PCI: 00:02.0 10 <- [0x00d0200000 - 0x00d027ffff] size 0x00080000 gran 0x13 mem
PCI: 00:02.0 14 <- [0x000000f070 - 0x000000f077] size 0x00000008 gran 0x03 io
PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem
PCI: 00:02.0 1c <- [0x00d0280000 - 0x00d02bffff] size 0x00040000 gran 0x12 mem
PCI: 00:1a.0 10 <- [0x00d02c4000 - 0x00d02c4fff] size 0x00001000 gran 0x0c mem
PCI: 00:1b.0 10 <- [0x00d02c0000 - 0x00d02c3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000e000 - 0x000000efff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00d0100000 - 0x00d01fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x000000e000 - 0x000000e0ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x00d0010000 - 0x00d0010fff] size 0x00001000 gran 0x0c prefmem64
PCI: 01:00.0 20 <- [0x00d0000000 - 0x00d000ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 01:00.0 30 <- [0x00d0100000 - 0x00d010ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1d.0 20 <- [0x000000f000 - 0x000000f01f] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x000000f020 - 0x000000f03f] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x000000f040 - 0x000000f05f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00d02c5000 - 0x00d02c53ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 10 <- [0x00d02c5400 - 0x00d02c54ff] size 0x00000100 gran 0x08 mem
PCI: 00:1e.1 10 <- [0x00d02c5500 - 0x00d02c55ff] size 0x00000100 gran 0x08 mem
PCI: 00:1e.2 10 <- [0x00d02c5600 - 0x00d02c56ff] size 0x00000100 gran 0x08 mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 164e.2 missing set_resources
PNP: 164e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 164e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 164e.7 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 20 <- [0x000000f060 - 0x000000f06f] size 0x00000010 gran 0x04 io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base e000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base c0000000 size 102c5700 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
PCI_DOMAIN: 0000 resource base c0000 size 3fffff40000 align 0 gran 0 limit 0 flags e0004200 index 4
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 0 flags f0000200 index 6
PCI_DOMAIN: 0000 resource base 3faf0000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:00.0
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:02.0
PCI: 00:02.0 resource base d0200000 size 80000 align 19 gran 19 limit dfffffff flags 60000200 index 10
PCI: 00:02.0 resource base f070 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60000200 index 18
PCI: 00:02.0 resource base d0280000 size 40000 align 18 gran 18 limit dfffffff flags 60000200 index 1c
PCI: 00:1a.0
PCI: 00:1a.0 resource base d02c4000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base d02c0000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base e000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.0 resource base d0000000 size 100000 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.0 resource base d0100000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base e000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
PCI: 01:00.0 resource base d0010000 size 1000 align 12 gran 12 limit dfffffff flags 60001201 index 18
PCI: 01:00.0 resource base d0000000 size 10000 align 16 gran 16 limit dfffffff flags 60001201 index 20
PCI: 01:00.0 resource base d0100000 size 10000 align 16 gran 16 limit dfffffff flags 60002200 index 30
PCI: 00:1c.1
PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.1 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.1 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 00:1d.0
PCI: 00:1d.0 resource base f000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
PCI: 00:1d.1
PCI: 00:1d.1 resource base f020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
PCI: 00:1d.2
PCI: 00:1d.2 resource base f040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
PCI: 00:1d.7
PCI: 00:1d.7 resource base d02c5000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 10
PCI: 00:1e.0
PCI: 00:1e.0 resource base d02c5400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:1e.1
PCI: 00:1e.1 resource base d02c5500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:1e.2
PCI: 00:1e.2 resource base d02c5600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:1f.0 child on link 0 PNP: 164e.2
PCI: 00:1f.0 resource base 0 size e000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 164e.2
PNP: 164e.2 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 164e.2 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 164e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index f1
PNP: 164e.3
PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 3ff flags e0000100 index 60
PNP: 164e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 164e.7
PNP: 164e.7 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 164e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PCI: 00:1f.1
PCI: 00:1f.1 resource base f060 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 07
PCI: 00:02.0 subsystem <- 0000/0000
PCI: 00:02.0 cmd <- 07
PCI: 00:1a.0 subsystem <- 0000/0000
PCI: 00:1a.0 cmd <- 02
PCI: 00:1b.0 subsystem <- 0000/0000
PCI: 00:1b.0 cmd <- 02
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 07
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 0000/0000
PCI: 00:1c.1 cmd <- 00
PCI: 00:1d.0 subsystem <- 0000/0000
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 subsystem <- 0000/0000
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 subsystem <- 0000/0000
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.7 subsystem <- 0000/0000
PCI: 00:1d.7 cmd <- 02
PCI: 00:1e.0 subsystem <- 0000/0000
PCI: 00:1e.0 cmd <- 06
PCI: 00:1e.1 subsystem <- 0000/0000
PCI: 00:1e.1 cmd <- 06
PCI: 00:1e.2 subsystem <- 0000/0000
PCI: 00:1e.2 cmd <- 06
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 03
PCI: 00:1f.1 subsystem <- 0000/0000
PCI: 00:1f.1 cmd <- 01
PCI: 01:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b
Initializing SMM handler... ... pmbase = 0x1040
SMI_STS:
PM1_STS:
GPE0_STS:
TCO_STS: TIMEOUT TCO_INT SW_TCO NMI2SMI
... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 106c2
CPU: family 06, model 1c, stepping 02
Using generic cpu ops (good)
Enabling cache
microcode_info: sig = 0x000106c2 pf=0x00000001 rev = 0x00000000
microcode updated to revision: 00000217 from revision 00000000
CPU: Intel(R) Atom(TM) CPU Z530 @ 1.60GHz.
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Zero-sized MTRR range @0KB
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x00 done.
CPU: 0 2 siblings
CPU: 0 has sibling 1
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
CPU: vendor Intel device 106c2
Waiting for send to finish...
CPU: family 06, model 1c, stepping 02
+Using generic cpu ops (good)
Sending STARTUP #2 to 1.
Enabling cache
After apic_write.
microcode_info: sig = 0xStartup point 1.
000106c2Waiting for send to finish...
pf=0x+00000001After Startup.
rev = 0xCPU #0 initialized
00000217Waiting for 1 CPUS to stop
microcode updated to revision: 00000217 from revision 00000217
CPU: Intel(R) Atom(TM) CPU Z530 @ 1.60GHz.
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Zero-sized MTRR range @0KB
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x01 done.
CPU: 1 2 siblings
CPU #1 initialized
CPU 1 going down...
All AP CPUs stopped
PCI: 00:02.0 init
PCI: 00:1a.0 init
USB Client: Setting up controller.. done.
PCI: 00:1b.0 init
sch_audio: base = d02c0000
sch_audio: codec_mask = 03
sch_audio: Initializing codec #1
sch_audio: GCAP: 01002200
sch_audio: OUTPAY: 001d003c
sch_audio: INPAY: 0001001d
sch_audio: codec viddid: 17e80047
sch_audio: dev=PCI: 00:1b.0
sch_audio: Reading viddid=17e80047
sch_audio: No verb!
sch_audio: Initializing codec #0
sch_audio: GCAP: 01002200
sch_audio: OUTPAY: 001d003c
sch_audio: INPAY: 0001001d
sch_audio: codec viddid: 83847682
sch_audio: dev=PCI: 00:1b.0
sch_audio: Reading viddid=83847682
sch_audio: No verb!
PCI: 00:1c.0 init
Initializing SCH PCIe bridge.
PCI: 00:1c.1 init
Initializing SCH PCIe bridge.
PCI: 00:1d.0 init
UHCI: Setting up controller.. PCI_COMMAND 5.
PCI_BASE f001.
PCI_FD 4.
done.
PCI: 00:1d.1 init
UHCI: Setting up controller.. PCI_COMMAND 5.
PCI_BASE f021.
PCI_FD 4.
done.
PCI: 00:1d.2 init
UHCI: Setting up controller.. PCI_COMMAND 5.
PCI_BASE f041.
PCI_FD 4.
done.
PCI: 00:1d.7 init
EHCI: Setting up controller.. PCI_COMMAND 100006.
PCI_BASE 0.
PCI_FD 0.
done.
PCI: 00:1e.0 init
MMC: Setting up controller.. done.
PCI: 00:1e.1 init
MMC: Setting up controller.. done.
PCI: 00:1e.2 init
MMC: Setting up controller.. done.
PCI: 00:1f.0 init
SCH: lpc_init
PCI: 00:1f.1 init
sch_ide: initializing... IDE0
PCI: 01:00.0 init
PNP: 164e.3 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1e.1: enabled 1
PCI: 00:1e.2: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 164e.2: enabled 1
PNP: 164e.3: enabled 1
PNP: 164e.7: enabled 1
PCI: 00:1f.1: enabled 1
PCI: 01:00.0: enabled 1
APIC: 01: enabled 1
ERROR: High Tables Base is not set.
High Tables Base is 0.
Adjust low_table_end from 0x00000500 to 0x00001000
Adjust rom_table_end from 0x000f0000 to 0x000f0000
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000000000-ffffffffffffffff: RESERVED
2. 0000000000001000-000000000009ffff: RAM
3. 00000000000c0000-00000000000effff: RAM
4. 00000000000f0000-00000000000effff: CONFIGURATION TABLES
5. 00000000000f0000-000000003faeffff: RAM
6. 000000003faf0000-000000003fafffff: RESERVED
7. 000000003fb00000-000003ffffffffff: RAM
Wrote coreboot table at: 00000500 - 000006f8 checksum 6e19
Check CBFS header at fffffd3e
magic is 4f524243
Found CBFS header at fffffd3e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 33e6 + align -> fff03440
Check fallback/coreboot_ram
CBFS: follow chain: fff03440 + 38 + d49e + align -> fff10940
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff10978
data (compression=1)
New segment dstaddr 0xe7bfc memsize 0x18404 srcaddr 0xfff109b0 filesize 0xbf63
(cleaned up) New segment addr 0xe7bfc size 0x18404 offset 0xfff109b0 filesize 0xbf63
Loading segment from rom address 0xfff10994
Entry Point 0x000fc903
Loading Segment: addr: 0x00000000000e7bfc memsz: 0x0000000000018404 filesz: 0x000000000000bf63
lb: [0x0000000000100000, 0x0000000000134000)
Post relocation: addr: 0x00000000000e7bfc memsz: 0x0000000000018404 filesz: 0x000000000000bf63
using LZMA
[ 0x000e7bfc, 00100000, 0x00100000) <- fff109b0
dest 000e7bfc, end 00100000, bouncebuffer fff98000
Loaded segments
Jumping to boot code at fc903
entry = 0x000fc903
lb_start = 0x00100000
lb_size = 0x00034000
adjust = 0xffecc000
buffer = 0xfff98000
elf_boot_notes = 0x001186a8
adjusted_boot_notes = 0xfffe46a8
-------------- next part --------------
make oldconfig
HOSTCC util/romcc/romcc (this may take a while)
printf " HOSTCC cbfstool/common.o\n"
HOSTCC cbfstool/common.o
gcc -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/cbfstool/common.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/common.c
gcc -g -Wall -o build/util/romcc/romcc /data/projects/Mdl/denhenk/work/coreboot/util/romcc/romcc.c
printf " HOSTCC cbfstool/compress.o\n"
printf " HOSTCXX cbfstool/minilzma.o\n"
HOSTCC cbfstool/compress.o
gcc -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/cbfstool/compress.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/compress.c
HOSTCXX cbfstool/minilzma.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/minilzma.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/minilzma.cc
printf " HOSTCXX cbfstool/LZMAEncoder.o\n"
printf " HOSTCXX cbfstool/LZInWindow.o\n"
HOSTCXX cbfstool/LZMAEncoder.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/LZMAEncoder.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/7zip/Compress/LZMA/LZMAEncoder.cpp
HOSTCXX cbfstool/LZInWindow.o
gcc -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -DCURSES_LOC="<ncurses.h>" -DLOCALE -c -o build/util/kconfig/conf.o /data/projects/Mdl/denhenk/work/coreboot/util/kconfig/conf.c
cp /data/projects/Mdl/denhenk/work/coreboot/util/kconfig/zconf.tab.c_shipped build/util/kconfig/zconf.tab.c
cp /data/projects/Mdl/denhenk/work/coreboot/util/kconfig/lex.zconf.c_shipped build/util/kconfig/lex.zconf.c
cp /data/projects/Mdl/denhenk/work/coreboot/util/kconfig/zconf.hash.c_shipped build/util/kconfig/zconf.hash.c
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/LZInWindow.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/7zip/Compress/LZ/LZInWindow.cpp
printf " HOSTCXX cbfstool/RangeCoderBit.o\n"
HOSTCXX cbfstool/RangeCoderBit.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/RangeCoderBit.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.cpp
gcc -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -DCURSES_LOC="<ncurses.h>" -DLOCALE -c -o build/util/kconfig/zconf.tab.o build/util/kconfig/zconf.tab.c
printf " HOSTCXX cbfstool/StreamUtils.o\n"
HOSTCXX cbfstool/StreamUtils.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/StreamUtils.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/7zip/Common/StreamUtils.cpp
printf " HOSTCXX cbfstool/OutBuffer.o\n"
HOSTCXX cbfstool/OutBuffer.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/OutBuffer.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/7zip/Common/OutBuffer.cpp
printf " HOSTCXX cbfstool/Alloc.o\n"
HOSTCXX cbfstool/Alloc.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/Alloc.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/Common/Alloc.cpp
printf " HOSTCXX cbfstool/CRC.o\n"
HOSTCXX cbfstool/CRC.o
g++ -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -c -o build/util/cbfstool/CRC.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/lzma/C/Common/CRC.cpp
printf " HOSTCC cbfstool/cbfs-mkstage.o\n"
printf " HOSTCC cbfstool/cbfs-mkpayload.o\n"
HOSTCC cbfstool/cbfs-mkstage.o
HOSTCC cbfstool/cbfs-mkpayload.o
gcc -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/cbfstool/cbfs-mkstage.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/cbfs-mkstage.c
gcc -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/cbfstool/cbfs-mkpayload.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/cbfs-mkpayload.c
printf " HOSTCC cbfstool/cbfstool.o\n"
HOSTCC cbfstool/cbfstool.o
gcc -DCOMPACT -g -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/cbfstool/cbfstool.o /data/projects/Mdl/denhenk/work/coreboot/util/cbfstool/cbfstool.c
GEN build.h
rm -f build/build.h
printf "/* build system definitions (autogenerated) */\n" > build/build.ht
printf "#ifndef __BUILD_H\n" >> build/build.ht
printf "#define __BUILD_H\n\n" >> build/build.ht
printf "#define COREBOOT_VERSION \"4.0-r17:52M\"\n" >> build/build.ht
printf "#define COREBOOT_EXTRA_VERSION \"-Mdl\"\n" >> build/build.ht
printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> build/build.ht
mkdir -p build/util/sconfig
mkdir -p build/util/sconfig/
cp /data/projects/Mdl/denhenk/work/coreboot/util/sconfig/sconfig.tab.h_shipped build/util/sconfig/sconfig.tab.h
mkdir -p build/util/sconfig/
cp /data/projects/Mdl/denhenk/work/coreboot/util/sconfig/lex.yy.c_shipped build/util/sconfig/lex.yy.c
mkdir -p build/util/sconfig/
printf "\n" >> build/build.ht
cp /data/projects/Mdl/denhenk/work/coreboot/util/sconfig/sconfig.tab.c_shipped build/util/sconfig/sconfig.tab.c
printf "#define COREBOOT_COMPILER \"gcc (Debian 4.3.2-1.1) 4.3.2\"\n" >> build/build.ht
printf "#define COREBOOT_ASSEMBLER \"GNU assembler (GNU Binutils for Debian) 2.18.0.20080103\"\n" >> build/build.ht
printf "#define COREBOOT_LINKER \"GNU ld (GNU Binutils for Debian) 2.18.0.20080103\"\n" >> build/build.ht
printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> build/build.ht
printf " HOSTCC util/sconfig/main.o\n"
HOSTCC util/sconfig/main.o
printf "#define COREBOOT_COMPILE_BY \"denhenk\"\n" >> build/build.ht
gcc -I/data/projects/Mdl/denhenk/work/coreboot/util/sconfig -Ibuild/util/sconfig -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/sconfig/main.o util/sconfig/main.c
printf "#define COREBOOT_COMPILE_HOST \"lnxdev01\"\n" >> build/build.ht
printf "#define COREBOOT_COMPILE_DOMAIN \"bk.Vndr.nl.\"\n" >> build/build.ht
printf "#endif\n" >> build/build.ht
mv build/build.ht build/build.h
CC romstage.inc
gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none -MMD -Isrc -Isrc/include -Ibuild -Isrc/arch/x86/include -Isrc/devices/oprom/include -include /data/projects/Mdl/denhenk/work/coreboot/build/config.h -Os -pipe -g -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wstrict-aliasing -Wshadow -Werror -nostdinc -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -D__PRE_RAM__ -Isrc -I. -Ibuild -c -S src/mainboard/Vndr/Mdl/romstage.c -o build/mainboard/Vndr/Mdl/romstage.pre.inc
HOSTCC sconfig/lex.yy.o
gcc -MMD -Iutil/sconfig/ -Ibuild/util/sconfig/ -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/sconfig/lex.yy.o build/util/sconfig/lex.yy.c
cc1: error: /data/projects/Mdl/denhenk/work/coreboot/build/config.h: No such file or directory
In file included from src/mainboard/Vndr/Mdl/romstage.c:23:
src/arch/x86/include/arch/romcc_io.h:10:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:68:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:77:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:87:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
src/arch/x86/include/arch/romcc_io.h:97:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:106:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:117:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
src/arch/x86/include/arch/romcc_io.h:128:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:137:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:148:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
src/arch/x86/include/arch/romcc_io.h:158:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:167:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:178:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
src/arch/x86/include/arch/romcc_io.h:189:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:198:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:209:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
src/arch/x86/include/arch/romcc_io.h:220:5: error: "CONFIG_PCI_IO_CFG_EXT" is not defined
src/arch/x86/include/arch/romcc_io.h:229:5: error: "CONFIG_MMCONF_SUPPORT" is not defined
src/arch/x86/include/arch/romcc_io.h:240:5: error: "CONFIG_MMCONF_SUPPORT_DEFAULT" is not defined
In file included from src/mainboard/Vndr/Mdl/romstage.c:23:
src/arch/x86/include/arch/romcc_io.h: In function 'pci_locate_device':
src/arch/x86/include/arch/romcc_io.h:262: error: 'CONFIG_PCI_BUS_SEGN_BITS' undeclared (first use in this function)
src/arch/x86/include/arch/romcc_io.h:262: error: (Each undeclared identifier is reported only once
src/arch/x86/include/arch/romcc_io.h:262: error: for each function it appears in.)
In file included from src/mainboard/Vndr/Mdl/romstage.c:26:
src/include/cpu/x86/lapic.h:9:5: error: "CONFIG_SMP" is not defined
src/include/cpu/x86/lapic.h:9:19: error: "CONFIG_IOAPIC" is not defined
src/include/cpu/x86/lapic.h:57:5: error: "CONFIG_AP_IN_SIPI_WAIT" is not defined
In file included from src/mainboard/Vndr/Mdl/romstage.c:29:
src/include/console/console.h:57:5: error: "CONFIG_CONSOLE_SERIAL8250" is not defined
In file included from src/mainboard/Vndr/Mdl/romstage.c:30:
src/include/cpu/x86/bist.h:7:5: error: "CONFIG_CACHE_AS_RAM" is not defined
In file included from src/mainboard/Vndr/Mdl/romstage.c:30:
src/include/cpu/x86/bist.h: In function 'report_bist_failure':
src/include/cpu/x86/bist.h:10: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
In file included from src/mainboard/Vndr/Mdl/romstage.c:281:
src/northbridge/intel/sch/early_init.c: In function 'sch_detect_chipset':
src/northbridge/intel/sch/early_init.c:143: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/northbridge/intel/sch/early_init.c: In function 'sch_setup_non_standard_bars':
src/northbridge/intel/sch/early_init.c:180: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
In file included from src/northbridge/intel/sch/raminit.c:21,
from src/mainboard/Vndr/Mdl/romstage.c:283:
src/include/cpu/x86/mtrr.h:57:3: error: #error "CONFIG_RAMTOP not defined"
src/include/cpu/x86/mtrr.h:67:6: error: "CONFIG_RAMTOP" is not defined
src/include/cpu/x86/mtrr.h:67:23: error: "CONFIG_RAMTOP" is not defined
In file included from src/mainboard/Vndr/Mdl/romstage.c:283:
src/northbridge/intel/sch/raminit.c: In function 'program_sch_dram_data':
src/northbridge/intel/sch/raminit.c:140: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/northbridge/intel/sch/raminit.c: In function 'do_jedec_init':
src/northbridge/intel/sch/raminit.c:225: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/northbridge/intel/sch/raminit.c: In function 'sdram_initialize':
src/northbridge/intel/sch/raminit.c:342: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/mainboard/Vndr/Mdl/romstage.c: In function 'sch_shadow_CMC':
src/mainboard/Vndr/Mdl/romstage.c:304: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/mainboard/Vndr/Mdl/romstage.c: In function 'poulsbo_setup_Stage1Regs':
src/mainboard/Vndr/Mdl/romstage.c:324: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/mainboard/Vndr/Mdl/romstage.c: In function 'poulsbo_setup_Stage2Regs':
src/mainboard/Vndr/Mdl/romstage.c:333: error: 'CONFIG_MAXIMUM_CONSOLE_LOGLEVEL' undeclared (first use in this function)
src/mainboard/Vndr/Mdl/romstage.c: In function 'main':
src/mainboard/Vndr/Mdl/romstage.c:353: error: 'CONFIG_TTYS0_BASE' undeclared (first use in this function)
cc1: warnings being treated as errors
src/mainboard/Vndr/Mdl/romstage.c:354: error: implicit declaration of function 'uart_init'
HOSTCC sconfig/sconfig.tab.o
gcc -MMD -Iutil/sconfig/ -Ibuild/util/sconfig/ -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -c -o build/util/sconfig/sconfig.tab.o build/util/sconfig/sconfig.tab.c
gcc -I/data/projects/Mdl/denhenk/work/coreboot/util/kconfig -Ibuild/util/kconfig -g -DCURSES_LOC="<ncurses.h>" -DLOCALE -o build/util/kconfig/conf build/util/kconfig/conf.o build/util/kconfig/zconf.tab.o
make: *** [build/mainboard/Vndr/Mdl/romstage.pre.inc] Error 1
make: *** Waiting for unfinished jobs....
build/util/kconfig/conf -o src/Kconfig
*
* coreboot Configuration
*
*
* General setup
*
Expert mode (EXPERT) [Y/n/?] y
Local version string (LOCALVERSION) [Mdl] Mdl
CBFS prefix to use (CBFS_PREFIX) [fallback] fallback
Compiler
> 1. GCC (COMPILER_GCC)
2. LLVM/clang (COMPILER_LLVM_CLANG)
choice[1-2?]: 1
Build with scan-build for static analysis (SCANBUILD_ENABLE) [N/y/?] n
ccache (CCACHE) [N/y/?] n
Generate SCONFIG parser using flex and bison (SCONFIG_GENPARSER) [N/y/?] n
*
* Mainboard
*
Mainboard vendor
1. Abit (VENDOR_ABIT)
2. Advantech (VENDOR_ADVANTECH)
3. AMD (VENDOR_AMD)
4. Arima (VENDOR_ARIMA)
5. Artec Group (VENDOR_ARTEC_GROUP)
6. ASI (VENDOR_ASI)
7. ASROCK (VENDOR_ASROCK)
8. ASUS (VENDOR_ASUS)
9. A-Trend (VENDOR_A_TREND)
10. AXUS (VENDOR_AXUS)
11. AZZA (VENDOR_AZZA)
12. BCOM (VENDOR_BCOM)
13. Biostar (VENDOR_BIOSTAR)
14. Broadcom (VENDOR_BROADCOM)
15. Compaq (VENDOR_COMPAQ)
16. Dell (VENDOR_DELL)
17. DIGITAL-LOGIC (VENDOR_DIGITAL_LOGIC)
18. EagleLion (VENDOR_EAGLELION)
19. ECS (VENDOR_ECS)
20. Emulation (VENDOR_EMULATION)
21. Getac (VENDOR_GETAC)
22. GIGABYTE (VENDOR_GIGABYTE)
23. HP (VENDOR_HP)
24. iBase (VENDOR_IBASE)
25. IBM (VENDOR_IBM)
26. IEI (VENDOR_IEI)
27. Intel (VENDOR_INTEL)
28. iWave (VENDOR_IWAVE)
29. IWILL (VENDOR_IWILL)
30. Jetway (VENDOR_JETWAY)
31. Kontron (VENDOR_KONTRON)
32. Lanner (VENDOR_LANNER)
33. Lenovo (VENDOR_LENOVO)
34. Lippert (VENDOR_LIPPERT)
35. Mitac (VENDOR_MITAC)
36. MSI (VENDOR_MSI)
37. NEC (VENDOR_NEC)
38. Newisys (VENDOR_NEWISYS)
39. Nokia (VENDOR_NOKIA)
40. NVIDIA (VENDOR_NVIDIA)
41. PC Engines (VENDOR_PC_ENGINES)
> 42. Vndr (VENDOR_Vndr)
43. RCA (VENDOR_RCA)
44. Roda (VENDOR_RODA)
45. Soyo (VENDOR_SOYO)
46. Sun (VENDOR_SUNW)
47. Supermicro (VENDOR_SUPERMICRO)
48. Technexion (VENDOR_TECHNEXION)
49. Technologic (VENDOR_TECHNOLOGIC)
50. TeleVideo (VENDOR_TELEVIDEO)
51. Thomson (VENDOR_THOMSON)
52. Traverse Technologies (VENDOR_TRAVERSE)
53. Tyan (VENDOR_TYAN)
54. VIA (VENDOR_VIA)
55. Win Enterprises (VENDOR_WINENT)
56. Wyse (VENDOR_WYSE)
choice[1-56]: 42
Mainboard model
> 1. Mdl (BOARD_Vndr_Mdl)
choice[1]: 1
ROM chip size
1. 128 KB (COREBOOT_ROMSIZE_KB_128)
2. 256 KB (COREBOOT_ROMSIZE_KB_256)
3. 512 KB (COREBOOT_ROMSIZE_KB_512)
> 4. 1024 KB (1 MB) (COREBOOT_ROMSIZE_KB_1024)
5. 2048 KB (2 MB) (COREBOOT_ROMSIZE_KB_2048)
6. 4096 KB (4 MB) (COREBOOT_ROMSIZE_KB_4096)
choice[1-6?]: 4
*
* Architecture (x86)
*
Bootblock behaviour
> 1. Always load fallback (X86_BOOTBLOCK_SIMPLE)
2. Switch to normal if CMOS says so (X86_BOOTBLOCK_NORMAL)
choice[1-2]: 1
Update existing coreboot.rom image (UPDATE_IMAGE) [N/y/?] n
*
* Chipset
*
*
* CPU
*
*
* Northbridge
*
*
* Southbridge
*
Add a CMC state machine binary (HAVE_CMC) [Y/n/?] y
Intel CMC path and filename (CMC_FILE) [microcode.bin] microcode.bin
*
* Super I/O
*
*
* Devices
*
Setup bridges on path to VGA adapter (VGA_BRIDGE_SETUP) [N/y/?] n
Run VGA option ROMs (VGA_ROM_RUN) [N/y/?] n
Run non-VGA option ROMs (PCI_ROM_RUN) [N/y/?] n
*
* Embedded Controllers
*
*
* Generic Drivers
*
Silicon Image SIL3114 (DRIVERS_SIL_3114) [Y/n/?] y
*
* Console
*
Serial port console output (CONSOLE_SERIAL8250) [Y/n/?] y
Serial port
> 1. COM1/ttyS0, I/O port 0x3f8 (CONSOLE_SERIAL_COM1)
2. COM2/ttyS1, I/O port 0x2f8 (CONSOLE_SERIAL_COM2)
3. COM3/ttyS2, I/O port 0x3e8 (CONSOLE_SERIAL_COM3)
4. COM4/ttyS3, I/O port 0x2e8 (CONSOLE_SERIAL_COM4)
choice[1-4]: 1
Baud rate
> 1. 115200 (CONSOLE_SERIAL_115200)
2. 57600 (CONSOLE_SERIAL_57600)
3. 38400 (CONSOLE_SERIAL_38400)
4. 19200 (CONSOLE_SERIAL_19200)
5. 9600 (CONSOLE_SERIAL_9600)
choice[1-5]: 1
USB 2.0 EHCI debug dongle support (USBDEBUG) [N/y/?] n
Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] n
Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K) [N/y/?] n
Maximum console log level
> 1. 8: SPEW (MAXIMUM_CONSOLE_LOGLEVEL_8)
2. 7: DEBUG (MAXIMUM_CONSOLE_LOGLEVEL_7)
3. 6: INFO (MAXIMUM_CONSOLE_LOGLEVEL_6)
4. 5: NOTICE (MAXIMUM_CONSOLE_LOGLEVEL_5)
5. 4: WARNING (MAXIMUM_CONSOLE_LOGLEVEL_4)
6. 3: ERR (MAXIMUM_CONSOLE_LOGLEVEL_3)
7. 2: CRIT (MAXIMUM_CONSOLE_LOGLEVEL_2)
8. 1: ALERT (MAXIMUM_CONSOLE_LOGLEVEL_1)
9. 0: EMERG (MAXIMUM_CONSOLE_LOGLEVEL_0)
choice[1-9]: 1
Default console log level
> 1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8)
2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7)
3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6)
4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5)
5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4)
6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3)
7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2)
8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1)
9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0)
choice[1-9]: 1
Don't show any POST codes (NO_POST) [N/y] n
Show POST codes on the debug console (CONSOLE_POST) [N/y/?] n
*
* System tables
*
Write 'high' tables to avoid being overwritten in F segment (WRITE_HIGH_TABLES) [N/y] n
Generate Multiboot tables (for GRUB2) (MULTIBOOT) [N/y] n
Generate ACPI tables (GENERATE_ACPI_TABLES) [N/y/?] n
Generate a PIRQ table (GENERATE_PIRQ_TABLE) [N/y/?] n
*
* Payload
*
Add a payload
1. None (PAYLOAD_NONE)
2. An ELF executable payload (PAYLOAD_ELF)
> 3. SeaBIOS (PAYLOAD_SEABIOS)
choice[1-3]: 3
SeaBIOS version
> 1. stable (SEABIOS_STABLE)
2. master (SEABIOS_MASTER)
choice[1-2]: 1
Use LZMA compression for payloads (COMPRESSED_PAYLOAD_LZMA) [Y/n/?] y
*
* VGA BIOS
*
Add a VGA BIOS image (VGA_BIOS) [N/y/?] n
*
* Debugging
*
GDB debugging support (GDB_STUB) [N/y/?] n
Output verbose SMI debug messages (DEBUG_SMI) [N/y/?] n
Debug SMM relocation code (DEBUG_SMM_RELOCATION) [N/y/?] n
Output verbose malloc debug messages (DEBUG_MALLOC) [N/y/?] n
Built-in low-level shell (LLSHELL) [N/y/?] n
*
* Deprecated
*
PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [N/y/?] n
#
# configuration written to .config
#
rm build/util/sconfig/sconfig.tab.c build/util/sconfig/lex.yy.c
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