[coreboot] Patch set updated: 1f23d3b Add voltage control of southbridge and RAM on ms7135

[Jonathan A. Kollasch (jakllsch@kollasch.net)]

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/126

-gerrit

commit 1f23d3b27abed80ee846807a2fe0421d72226679
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Mon Aug 1 14:24:02 2011 -0500

    Add voltage control of southbridge and RAM on ms7135
    
    Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/mainboard/msi/ms7135/cmos.layout |   16 +++++++++++--
 src/mainboard/msi/ms7135/romstage.c  |   39 +++++++++++++++++++++++++--------
 2 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout
index 53fdef5..694554d 100644
--- a/src/mainboard/msi/ms7135/cmos.layout
+++ b/src/mainboard/msi/ms7135/cmos.layout
@@ -43,6 +43,8 @@ entries
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu
+448          4       e      10        ram_voltage
+452          4       e      11        nf4_voltage
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
@@ -74,10 +76,10 @@ enumerations
 7     0     Network
 7     1     HDD
 7     2     Floppy
+#7     3     ROM
 7     8     Fallback_Network
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
-#7     3     ROM
 8     0     400Mhz
 8     1     333Mhz
 8     2     266Mhz
@@ -91,8 +93,16 @@ enumerations
 9     6     25.0%
 9     7     12.5%
 
-checksums
+10    0     2.55
+10    1     2.50
+10    2     2.60
+10    3     2.65
+10    4     2.70
 
-checksum 392 983 984
+11    0     1.50
+11    1     1.55
+11    2     1.60
 
+checksums
 
+checksum 392 983 984
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 8609142..1b1c119 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -48,6 +48,10 @@
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
 
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
+
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -66,6 +70,27 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
+static void ms7135_set_ram_voltage(void)
+{
+	u8 b;
+	b = read_option(ram_voltage, 0);
+	if (b > 4) /* default if above 2.70v */
+		b = 0;
+	printk(BIOS_INFO, "setting RAM voltage %08x\n", b);
+	ck804_smbus_write_byte(1, 0x2f, 0x00, b);
+}
+
+static void ms7135_set_nf4_voltage(void)
+{
+	u8 b;
+	b = read_option(nf4_voltage, 0);
+	if (b > 2) /* default if above 1.60v */
+		b = 0;
+	b |= 0x10;
+	printk(BIOS_INFO, "setting NF4 voltage %08x\n", b);
+	ck804_smbus_write_byte(1, 0x2f, 0x02, b);
+}
+
 static void sio_setup(void)
 {
 	uint32_t dword;
@@ -112,10 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
 	needs_reset = setup_coherent_ht_domain();
 
 	wait_all_core0_started();
@@ -140,17 +161,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();
 
-#if 0
+	ms7135_set_nf4_voltage();
+	ms7135_set_ram_voltage();
+
+#if CONFIG_DEBUG_SMBUS
 	dump_spd_registers(&ctrl[0]);
 	dump_smbus_registers();
 #endif
 
 	sdram_initialize(nodes, ctrl);
 
-#if 0
-	print_pci_devices();
-	dump_pci_devices();
-#endif
-
 	post_cache_as_ram();
 }