[coreboot] New patch to review: efa4eab smbus: Example of how to use generic smbus code
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Tue Aug 9 09:05:12 CEST 2011
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/144
-gerrit
commit efa4eabbf4a197726d351685d48b61edfa202f06
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Tue Aug 9 02:00:43 2011 -0500
smbus: Example of how to use generic smbus code
NOTFORMERGE
Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/northbridge/via/vx900/Kconfig | 23 ++++
src/northbridge/via/vx900/Makefile.inc | 33 +++++
src/northbridge/via/vx900/early_smbus.c | 194 +++++++++++++++++++++++++++++++
src/northbridge/via/vx900/early_vx900.h | 31 +++++
src/northbridge/via/vx900/romstrap.inc | 50 ++++++++
src/northbridge/via/vx900/romstrap.lds | 27 +++++
src/northbridge/via/vx900/vx900.h | 26 ++++
7 files changed, 384 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
new file mode 100644
index 0000000..60e7993
--- /dev/null
+++ b/src/northbridge/via/vx900/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+config NORTHBRIDGE_VIA_VX900
+ bool
+ select HAVE_DEBUG_RAM_SETUP
+ select HAVE_DEBUG_SMBUS
\ No newline at end of file
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
new file mode 100644
index 0000000..5450b1d
--- /dev/null
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+romstage-y += early_smbus.c
+romstage-y += raminit_ddr3.c
+romstage-y += ./../../../devices/dram/dram_util.c
+romstage-y += ./../../../devices/smbus/early_smbus.c
+
+# Drivers for these devices already exist with the vx800
+# Use those instead of duplicating code
+
+driver-y += ./../vx800/northbridge.c
+driver-y += ./../vx800/vga.c
+driver-y += ./../vx800/lpc.c
+
+chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
+chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds
\ No newline at end of file
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
new file mode 100644
index 0000000..707bd10
--- /dev/null
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <device/pci_ids.h>
+#include "early_vx900.h"
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <devices/dram/dram.h>
+
+#define SMBUS_IO_BASE 0x500
+#include <devices/smbus/smbus.h>
+
+__attribute__((unused))
+static void smbus_delays(int delays)
+{
+ while(delays--) __smbus_delay();
+}
+
+
+/**
+ * Read a byte from the SMBus.
+ *
+ * @param dimm The address location of the DIMM on the SMBus.
+ * @param offset The offset the data is located at.
+ */
+u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base)
+{
+ u8 val;
+
+ /* Initialize SMBUS sequence */
+ smbus_reset();
+ /* Clear host data port. */
+ outb(0x00, SMBHSTDAT0);
+
+ smbus_wait_until_ready();
+ smbus_delays(50);
+
+ /* Actual addr to reg format. */
+ dimm = (dimm << 1);
+ dimm |= 1; /* read command */
+ outb(dimm, SMBXMITADD);
+ outb(offset, SMBHSTCMD);
+ /* Start transaction, byte data read. */
+ outb(0x48, SMBHSTCTL);
+ smbus_wait_until_ready();
+
+ val = inb(SMBHSTDAT0);
+ return val;
+}
+
+void enable_smbus(void)
+{
+ device_t dev;
+ u8 reg8;
+ u16 __smbus_io_base = SMBUS_IO_BASE;
+
+ /* Locate the Power Management control */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID) {
+ die("Power Managment Controller not found\n");
+ }
+
+ /*
+ * To use SMBus to manage devices on the system board, it is a must to
+ * enable SMBus function by setting
+ * PMU_RXD2[0] (SMBus Controller Enable) to 1.
+ * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate
+ * I/O port address, so that all registers in SMBus I/O port can be
+ * accessed.
+ */
+
+ reg8 = pci_read_config8(dev, 0xd2);
+ /* Enable SMBus controller */
+ reg8 |= 1;
+ /* Set SMBUS clock from 128k source */
+ reg8 |= 1<<2;
+ pci_write_config8(dev, 0xd2, reg8);
+
+ reg8 = pci_read_config8(dev, 0x94);
+ /* SMBUS clock from divider of 14.318 MHz */
+ reg8 &= ~(1<<7);
+ pci_write_config8(dev, 0x94, reg8);
+
+ /* Set SMBus IO base */
+ pci_write_config16(dev, 0xd0, SMBUS_IO_BASE);
+
+ /*
+ * Initialize the SMBus sequence:
+ */
+ /* Clear SMBus host status register */
+ smbus_reset();
+ /* Clear SMBus host data 0 register */
+ outb(0x00, SMBHSTDAT0);
+
+ /* Wait for SMBUS */
+ smbus_wait_until_ready();
+
+}
+
+void spd_read(u8 addr, spd_raw_data spd)
+{
+ u8 reg;
+ int i, regs;
+ reg = smbus_read_byte(addr, 2);
+ if(reg != 0x0b)
+ {
+ printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr);
+ spd[2] = 0;
+ return;
+ }
+
+ reg = smbus_read_byte(addr, 0);
+ reg &= 0xf;
+ if (reg == 0x3) {
+ regs = 256;
+ } else if (reg == 0x2) {
+ regs = 176;
+ } else if (reg == 0x1) {
+ regs = 128;
+ } else {
+ printk(BIOS_INFO, "No DIMM present at %x\n", addr);
+ spd[2] = 0;
+ return;
+ }
+ printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", addr);
+ for (i = 0; i < regs; i++) {
+ reg = smbus_read_byte(addr, i);
+ //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", i, reg );
+ spd[i] = reg;
+ }
+}
+
+void dump_spd_data(void)
+{
+ int dimm, offset, regs;
+ unsigned int reg;
+ spd_raw_data spd;
+ dimm_attr dimmx;
+
+ for (dimm = 0x50; dimm < 0x52; dimm++) {
+ reg = smbus_read_byte(dimm, 2);
+ if(reg != 0x0b)
+ {
+ printk(BIOS_DEBUG,
+ "SMBUS device %x not a DDR3 module\n", dimm);
+ continue;
+ }
+
+ reg = smbus_read_byte(dimm, 0);
+ reg &= 0xf;
+ if (reg == 0x3) {
+ regs = 256;
+ } else if (reg == 0x2) {
+ regs = 176;
+ } else if (reg == 0x1) {
+ regs = 128;
+ } else {
+ printk(BIOS_INFO, "No DIMM present at %x\n", dimm);
+ regs = 0;
+ continue;
+ }
+ printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", dimm);
+ for (offset = 0; offset < regs; offset++) {
+ reg = smbus_read_byte(dimm, offset);
+ //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", offset, reg );
+ spd[offset] = reg;
+ }
+
+ spd_decode_ddr3(&dimmx, spd);
+ dram_print_spd_ddr3(&dimmx);
+
+ }
+}
+
diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h
new file mode 100644
index 0000000..798cac0
--- /dev/null
+++ b/src/northbridge/via/vx900/early_vx900.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef EARLY_VX900_H
+#define EARLY_VX900_H
+
+#include <stdint.h>
+
+#include "raminit.h"
+
+void enable_smbus(void);
+void dump_spd_data(void);
+void spd_read(u8 addr, spd_raw_data spd);
+
+#endif /* EARLY_VX900_H */
diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc
new file mode 100644
index 0000000..8e54627
--- /dev/null
+++ b/src/northbridge/via/vx900/romstrap.inc
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer)
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file constructs the ROM strap table for VX900 */
+
+ .section ".romstrap", "a", @progbits
+
+ .globl __romstrap_start
+__romstrap_start:
+tblpointer:
+ .long 0x77886047
+ .long 0x00777777
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00888888
+ .long 0x00AA1111
+ .long 0x00000000
+ .long 0x00000000
+
+/*
+ * The pointer to above table should be at 0xffffffd0,
+ * the table itself MUST be aligned to 128B it seems!
+ */
+rspointers:
+ .long tblpointer // It will be 0xffffffd0
+
+ .globl __romstrap_end
+
+__romstrap_end:
+.previous
diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds
new file mode 100644
index 0000000..b51c979
--- /dev/null
+++ b/src/northbridge/via/vx900/romstrap.lds
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>
+ */
+
+SECTIONS {
+ . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start);
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
new file mode 100644
index 0000000..2137daf
--- /dev/null
+++ b/src/northbridge/via/vx900/vx900.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define VX800_ACPI_IO_BASE 0x0400
+
+#define VX900_NB_IOAPIC_ID 0x2
+#define VX900_NB_IOAPIC_BASE 0xfecc000
+
+#define VX900_SB_IOAPIC_ID 0x1
+#define VX900_SB_IOAPIC_BASE 0xfec0000
\ No newline at end of file
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