[coreboot] [PATCH] RFC AMD powernow generation for pre fam 0fh

[Stefan Reinauer]

* Rudolf Marek <r.marek at assembler.cz> [110224 21:04]:
> Hi all
> 
> Attaching update patch. Not much changed,  only comments added.
> 
> It adds support for automatic PSS object generation for AMD pre fam
> Fh CPU. Those CPUs require a hardcoded table, which I managed to
> rewrite during one particularly boring flight. Too pity it is only
> for Opteron CPUs. Someone needs to finish the second PDF for All
> others Athlons and Semprons.
> 
> Also it enables the FID/VID changes in SB. Jakllsch had some
> troubles with that too but on am2 CPU. Those bits are only
> documented in SB600. They arent in RRG RPR and BDG.
> 
> Signed-off-by:Rudolf Marek <r.marek at asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

> 
> Thanks,
> Rudolf

Stefan