[coreboot] IDE interface support code for AMDLX800-CS5536

[Darmawan Salihun]

Hi guys,

I'm looking for the support code for the IDE controller in CS5536 southbridge.
I checked-out Coreboot source code but only saw Flash interface
support in there.
I saw the IDE controller is switched to Flash interface support with
the "DEADBEEF"
magic number.

The board I'm working with right now use the primary IDE channel for both
HDD connectors and a CF connectors. I need to know how to initialize
the chipset
correctly for this setup. The CF connector is the primary master and
the HDD connector is primary slave.

I've checked with lspci and " cat /proc/ioports" and I found that the
legacy I/O ports
for IDE controller is working just fine. Also, the I/O ports for
IDE bus mastering (SFF-8038i) registers are allocated correctly.

Thanks,

Darmawan
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