[coreboot] Jetw. J8F9 support
Cristian Craciunescu
ccristian at gmail.com
Tue Jan 18 09:37:39 CET 2011
Patch bellow:
Index: src/superio/fintek/Kconfig
===================================================================
--- src/superio/fintek/Kconfig (revision 6237)
+++ src/superio/fintek/Kconfig (working copy)
@@ -27,3 +27,5 @@
bool
config SUPERIO_FINTEK_F71889
bool
+config SUPERIO_FINTEK_F81216
+ bool
Index: src/superio/fintek/Makefile.inc
===================================================================
--- src/superio/fintek/Makefile.inc (revision 6237)
+++ src/superio/fintek/Makefile.inc (working copy)
@@ -22,3 +22,4 @@
subdirs-y += f71863fg
subdirs-y += f71872
subdirs-y += f71889
+subdirs-y += f81216
Index: src/superio/fintek/f81216/Makefile.inc
===================================================================
--- src/superio/fintek/f81216/Makefile.inc (revision 0)
+++ src/superio/fintek/f81216/Makefile.inc (revision 0)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <corey.osgood at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+##
+
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81216) += superio.c
+
Index: src/superio/fintek/f81216/superio.c
===================================================================
--- src/superio/fintek/f81216/superio.c (revision 0)
+++ src/superio/fintek/f81216/superio.c (revision 0)
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <uart8250.h>
+#include "chip.h"
+#include "f81216.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x77, dev->path.pnp.port);
+ outb(0x77, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
+static void f81216_init(device_t dev)
+{
+ struct superio_fintek_f81216_config *conf = dev->chip_info;
+ struct resource *res0;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.pnp.device) {
+ /* TODO: Might potentially need code for HWM or FDC etc. */
+ case F81216_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case F81216_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ case F81216_SP3:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com3);
+ break;
+ case F81216_SP4:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com4);
+ break;
+ }
+}
+
+static void f81216_pnp_set_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void f81216_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void f81216_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_exit_conf_state(dev);
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = f81216_pnp_set_resources,
+ .enable_resources = f81216_pnp_enable_resources,
+ .enable = f81216_pnp_enable,
+ .init = f81216_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ /* TODO: Some of the 0x07f8 etc. values may not be correct. */
+ { &ops, F81216_SP1, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, F81216_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216_SP4, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f81216_ops = {
+ CHIP_NAME("Fintek F81216 Super I/O")
+ .enable_dev = enable_dev
+};
Index: src/superio/fintek/f81216/chip.h
===================================================================
--- src/superio/fintek/f81216/chip.h (revision 0)
+++ src/superio/fintek/f81216/chip.h (revision 0)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#ifndef SUPERIO_FINTEK_F81216_CHIP_H
+#define SUPERIO_FINTEK_F81216_CHIP_H
+
+#include <device/device.h>
+#include <uart8250.h>
+
+/* This chip doesn't have keyboard and mouse support. */
+
+extern struct chip_operations superio_fintek_f81216_ops;
+
+struct superio_fintek_f81216_config {
+ struct uart8250 com1, com2, com3, com4;
+};
+
+#endif
Index: src/superio/fintek/f81216/early_serial.c
===================================================================
--- src/superio/fintek/f81216/early_serial.c (revision 0)
+++ src/superio/fintek/f81216/early_serial.c (revision 0)
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f81216.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x77, port);
+ outb(0x77, port);
+}
+
+/*
+ * Acording to documentation of Fintek device
+ * we must set the clock option first(we set 48Mhz)
+ */
+static void pnp_set_clock(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x25, port);
+ outb(0x01, port + 1);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f81216_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_clock(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
Index: src/superio/fintek/f81216/f81216.h
===================================================================
--- src/superio/fintek/f81216/f81216.h (revision 0)
+++ src/superio/fintek/f81216/f81216.h (revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#ifndef SUPERIO_FINTEK_F81216_H
+#define SUPERIO_FINTEK_F81216_H
+
+/*
+ * Datasheet:
+ * - Name: F71805F/FG Super H/W Monitor + LPC IO
+ * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17
+ * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf
+ * - Revision: V0.25P
+ */
+
+/* Logical Device Numbers (LDN). */
+#define F81216_SP1 0x00 /* UART1 */
+#define F81216_SP2 0x01 /* UART2 */
+#define F81216_SP3 0x02 /* UART3 */
+#define F81216_SP4 0x03 /* UART4 */
+
+#endif
Index: src/mainboard/jetway/Kconfig
===================================================================
--- src/mainboard/jetway/Kconfig (revision 6237)
+++ src/mainboard/jetway/Kconfig (working copy)
@@ -7,11 +7,14 @@
bool "J7F24"
config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)"
+config BOARD_JETWAY_J8
+ bool "J8 Nano-ITX"
endchoice
source "src/mainboard/jetway/j7f24/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig"
+source "src/mainboard/jetway/j8/Kconfig"
config MAINBOARD_VENDOR
string
Index: src/mainboard/jetway/j8/Kconfig
===================================================================
--- src/mainboard/jetway/j8/Kconfig (revision 0)
+++ src/mainboard/jetway/j8/Kconfig (revision 0)
@@ -0,0 +1,28 @@
+if BOARD_JETWAY_J8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+# select SUPERIO_WINBOND_W83627HF
+ select SUPERIO_FINTEK_F81216
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select BOARD_ROMSIZE_KB_256
+ select POWER_BUTTON_FORCE_ENABLE
+
+config MAINBOARD_DIR
+ string
+ default jetway/j8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PCISA-LX-800-R10"
+
+config IRQ_SLOT_COUNT
+ int
+ default 9
+
+endif # BOARD_JETWAY_J8
Index: src/mainboard/jetway/j8/devicetree.cb
===================================================================
--- src/mainboard/jetway/j8/devicetree.cb (revision 0)
+++ src/mainboard/jetway/j8/devicetree.cb (revision 0)
@@ -0,0 +1,58 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and
Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x000011fa"
+ register "lpc_serirq_polarity" = "0x0000EF05"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off,
xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci d.0 on end # Ethernet 1
+ device pci f.0 on # ISA Bridge
+ chip superio/fintek/f81216
+ device pnp 4e.0 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.1 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.2 on # Com3
+ io 0x60 = 0x3e8
+ irq 0x70 = 5
+ end
+ device pnp 4e.3 on # Com4
+ io 0x60 = 0x2e8
+ irq 0x70 = 7
+ end
+ end
+ end
+
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device lapic_cluster 0 on
+ chip cpu/amd/model_lx
+ device lapic 0 on end
+ end
+ end
+end
+
Index: src/mainboard/jetway/j8/romstage.c
===================================================================
--- src/mainboard/jetway/j8/romstage.c (revision 0)
+++ src/mainboard/jetway/j8/romstage.c (revision 0)
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/geode_post_code.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "superio/fintek/f81216/early_serial.c"
+#include "arch/x86/include/arch/llshell.h"
+
+#define SERIAL_DEV PNP_DEV(0x4e, F81216_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#define ManualConf 1 /* Do automatic strapped PLL config */
+#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
+////#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
+//#define PLLMSRhi 0x0000049e
+//#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
+//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
+/* Hold Count - how long we will sit in reset */
+#define PLLMSRlo 0x00DE6000
+
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
+
+void main(unsigned long bist)
+{
+ post_code(0x01);
+
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ // Cristi
+ // Need to initialize the Fintek superio for serials
+ //
+ f81216_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset(ManualConf);
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+ llshell();
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+ return;
+}
Index: src/mainboard/jetway/j8/irq_tables.c
===================================================================
--- src/mainboard/jetway/j8/irq_tables.c (revision 0)
+++ src/mainboard/jetway/j8/irq_tables.c (revision 0)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 5
+#define PIRQC 10
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total
CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0xc00, /* IRQs devoted exclusively to PCI usage */
+ 0x100b, /* Vendor */
+ 0x2b, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xe, /* u8 checksum. This has to be set to some
+ value that would give 0 after the sum of all
+ bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link,
bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00,
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x0f<<3)|0x0, {{0x00, 0x0000}, {0x02, 0x0400}, {0x00,
0x0000}, {0x04, 0x00400}}, 0x0, 0x0},
+ {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00,
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00,
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00,
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03,
0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04,
0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01,
0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
+ {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02,
0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/jetway/j8/chip.h
===================================================================
--- src/mainboard/jetway/j8/chip.h (revision 0)
+++ src/mainboard/jetway/j8/chip.h (revision 0)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
Index: src/mainboard/jetway/j8/mainboard.c
===================================================================
--- src/mainboard/jetway/j8/mainboard.c (revision 0)
+++ src/mainboard/jetway/j8/mainboard.c (revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Jetway LX-800 Mainboard")
+};
Index: src/northbridge/amd/lx/northbridge.c
===================================================================
--- src/northbridge/amd/lx/northbridge.c (revision 6237)
+++ src/northbridge/amd/lx/northbridge.c (working copy)
@@ -412,11 +412,11 @@
cpubug();
chipsetinit();
- // print_conf();
+ print_conf();
do_vsmbios(); // do the magic stuff here, so prepare your
tambourine ;)
- // print_conf();
+ print_conf();
graphics_init();
pci_set_method(dev);
On Tue, Jan 18, 2011 at 10:28 AM, Cristian Craciunescu
<ccristian at gmail.com>wrote:
> I'm sure the problem is coming from PIRQ map; needs some fine tuning. The
> board has four serials and all of them are connected the 81216DG super IO
> chip so I'm using the first serial port, the onchip uarts are disabled.
> There is an additional hwmon chip(f71858) which I did not touched
> yet. Attached the patch with j8 dir in mainboard and f81216DG superio
> added.
>
>
>
>
> Regards,
> Cristian
> On Tue, Jan 18, 2011 at 10:01 AM, Cristian Craciunescu
> <ccristian at gmail.com>wrote <ccristian at gmail.com%3Ewrote>:
>
> > Cristian Craciunescu wrote:
> > > I've compiled suport for j8f9 board from jetw. using as template other
> LX
> > > mainboard. The system is booting with coreboot/seabios however the
> serial
> > > does not seam to work in kernel. GRUB bootloader works ok over serial
> but
> > as
> > > soon as the linux kernel finish booting it does not respond over serial
> > but
> > > it can send messages to serial. Although the IRQs are detected
> correctly
> > > when the serial has input I can not see any irq messages incrementing
> in
> > > /proc/interrupts. Any hint?
> >
> > Something is wrong with the interrupt setup in coreboot if they are
> > not being delivered to the kernel.
> >
> > Are you using the internal UART in CS5536 or do you have a superio?
> > Which board did you use as template?
> > Can you post a patch with your code so far?
> >
> >
> > //Peter
> >
>
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