[coreboot] [commit] r6276 - trunk/src/northbridge/amd/amdmct/mct_ddr3

[repository service]

Author: zbao
Date: Thu Jan 20 03:09:24 2011
New Revision: 6276
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6276

Log:
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	Wed Jan 19 08:25:26 2011	(r6275)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c	Thu Jan 20 03:09:24 2011	(r6276)
@@ -306,7 +306,7 @@
 				if (!(pDCTstat->Status & (1 << SB_Registered)))
 					break; /* For UDIMM, only send MR commands once per channel */
 		}
-		if (pDCTstat->LogicalCPUID & (AMD_DR_Cx/* | AMD_RB_C0 */)) /* We dont support RB_C0 now. need to be added and tested. */
+		if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0 */)) /* TODO: We dont support RB_C0 now. need to be added and tested. */
 			if (!(pDCTstat->Status & (1 << SB_Registered)))
 				MrsChipSel ++;
 	}