[coreboot] [commit] r6614 - in trunk/src: southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800

repository service svn at coreboot.org
Wed Jun 1 04:00:30 CEST 2011


Author: kerry
Date: Wed Jun  1 04:00:30 2011
New Revision: 6614
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6614

Log:
trivial remove blanks at the end of line

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Kerry She <kerry.she at amd.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
   trunk/src/vendorcode/amd/cimx/sb800/SATA.c

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Wed Jun  1 03:56:49 2011	(r6613)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Wed Jun  1 04:00:30 2011	(r6614)
@@ -27,7 +27,7 @@
 #include "lpc.h"		/* lpc_read_resources */
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
-#include "chip.h" 		/* struct southbridge_amd_cimx_wrapper_sb800_config */
+#include "chip.h"		/* struct southbridge_amd_cimx_wrapper_sb800_config */
 
 
 /*implement in mainboard.c*/
@@ -363,7 +363,7 @@
 	    /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 	    setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 	    #elif (CONFIG_APIC_ID_OFFSET > 0)
-	    /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ 
+	    /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 	    setup_ioapic(ioapic_base, 0);
 	    #else
 	    #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"

Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Wed Jun  1 03:56:49 2011	(r6613)
+++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Wed Jun  1 04:00:30 2011	(r6614)
@@ -43,7 +43,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include "SBPLATFORM.h"
 #include "cbtypes.h"
 
@@ -317,7 +317,7 @@
   }
   if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
     ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
-    if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {    
+    if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
       ddTempVar = pConfig->BuildParameters.SataAHCISsid;
     }
   }




More information about the coreboot mailing list