[coreboot] Questions about coreboot on X86

[Patrick Georgi]

On Tue, 14 Jun 2011 22:44:20 +0800, Hamo wrote:
> 2. What's the propose of romstage? Some init in romstage has been 
> done
> in bootblock, and why those init are done twice?
Historical reasons.

First, coreboot had two parts: bootblock/romstage (which was a single 
entity) and ramstage.
The romstage did raminit and generally set things up so the ramstage 
could work.
As only the top 64kb of flash are guaranteed to be mapped into memory 
space, it was also responsible for mapping the entire flash.

Then came AMD K8.

Its memory init was more complicated (with all the HyperTransport 
setup) and thus exceeded the 64kb the romstage lived in, so things were 
split up.
At some point we moved things around so there's a tiny bootblock (doing 
only flash mapping and maybe deciding which romstage to load), and the 
romstage doing raminit until the ramstage can be loaded as usual.

Many boards are converted to that new style. As it requires chipset 
modifications (essentially splitting out the flash mapping code), some 
boards were not.
At some point I hope we'll have all boards follow the new style.

It might not be necessary for ARM, but I'd propose you also stick to 
the general layout:
- bootblock does flash mapping (if necessary) and decides which 
romstage to load
- romstage does raminit
- ramstage does businit
- payload does whatever is necessary next.


Patrick