[coreboot] New patch to review: d22355c ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic

[Marshall Buschman (mbuschman@lucidmachines.com)]

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/44

-gerrit

commit d22355cefabca65598a37ef8e0438d89c382174d
Author: Scott Duplichan <scott at notabs.org>
Date:   Sat Jun 18 10:46:45 2011 -0500

    ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
    
    Scott Duplichan's patch from the mailing list:
    sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
    once, after determining device 0x15 function enables.
    
    1) Update the asrock e350m1 devicetree.cb to match the hardware.
    2) Change the way the sb800 cimx wrapper code works. The original
    cimx code calls sb800 cimx function sbBeforePciInit() once. When
    ported to coreboot, the gpp component of this function was called
    once for each gpp port, as the gpp port's enable/disable state
    became known. A 05/15/2011 change makes the early gpp code run
    only once, triggered by processing the 4th gpp port. This method
    is not general enough because the 4th gpp port is not enabled on
    all boards. With the current change, the early gpp code runs when
    the first gpp port is processed. If any gpp ports are enabled, the
    first must be enabled. Tested with Win7 and linux on asrock e350m1.
    This change will also affect amd inagua, and has not been tested
    on that board.
    
    Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
    Signed-off-by: Scott Duplichan <scott at notabs.org>
    Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/devicetree.cb     |   14 +++++++++--
 src/southbridge/amd/cimx_wrapper/sb800/late.c |   31 +++++++++----------------
 2 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index d1e4a8b..bc3bd18 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -99,11 +99,19 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
 					end #LPC
   					device pci 14.4 on end # PCI 0x4384
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 off end # PCIe PortA
-					device pci 15.1 off end # PCIe PortB
+					device pci 15.0 on  end # PCIe PortA
+					device pci 15.1 on  end # PCIe PortB
 					device pci 15.2 off end # PCIe PortC
 					device pci 15.3 off end # PCIe PortD
-					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+
+					# gpp_configuration options
+					#0000: PortA lanes[3:0]
+					#0001: N/A
+					#0010: PortA lanes[1:0], PortB lanes[3:2]
+					#0011: PortA lanes[1:0], PortB lane2, PortC lane3
+					#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
+					register "gpp_configuration" = "4"
+
  		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c
index 50eeb48..6926443 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c
@@ -413,16 +413,13 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
-		sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
-		sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
-		sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-		sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
+		{
+		device_t device;
+		for (device = dev; device; device = device->next) {
+			if (dev->path.type != DEVICE_PATH_PCI) continue;
+			if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
+			sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+		}
 
 		/*
 		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
@@ -430,22 +427,16 @@ static void sb800_enable(device_t dev)
 		 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 		 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 		 */
-		if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
-			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
-		}
-
-		sbPcieGppEarlyInit(sb_config);
+		sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+		sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+		AmdSbDispatcher(sb_config);
 		break;
+		}
 
 	default:
 		break;
 	}
 
-	/* Special setting ABCFG registers before PCI emulation. */
-	abSpecialSetBeforePciEnum(sb_config);
-  	usbDesertPll(sb_config);
-	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
-	//AmdSbDispatcher(sb_config);
 }
 
 struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {